diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2023-04-17 22:07:20 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-04-21 10:16:01 +0300 |
| commit | 6737771600d4fd8eb48663ea8da37f3f4f49aad5 (patch) | |
| tree | 687751891c437114ecf071e2697a1ae23406de5d /arch/arm/include/asm | |
| parent | 22297581187c346740d5af4ee603701142b58fd6 (diff) | |
| download | u-boot-6737771600d4fd8eb48663ea8da37f3f4f49aad5.tar.xz | |
rockchip: rk3588: Add support for sdmmc clocks in SPL
Booting from sdmmc on RK3588 currently works because of a workaround in
the device tree, clocks are reordered so that the driver use ciu-sample
instead of ciu, and the BootRom initializes sdmmc clocks before SPL is
loaded into DRAM.
The sdmmc clocks are normally controlled by TF-A using SCMI. However,
there is a need to control these clocks in SPL, before TF-A has started.
This adds a rk3588_scru driver to control the sdmmc clocks in SPL before
TF-A has started, using scru regs. It also adds a small glue driver to
bind the scmi clock node to the rk3588_scru driver in SPL.
Fixes: 7a474df74023 ("clk: rockchip: Add rk3588 clk support")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/cru_rk3588.h | 19 |
2 files changed, 18 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 90e66c7da0..f002ebcb7a 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -194,6 +194,5 @@ int rockchip_get_clk(struct udevice **devp); * Return: 0 success, or error value */ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number); -int rockchip_get_scmi_clk(struct udevice **devp); #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h index 3ea59e9008..7f4a908539 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3588.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3588.h @@ -11,12 +11,12 @@ #define KHz 1000 #define OSC_HZ (24 * MHz) -#define CPU_PVTPLL_HZ (1008 * MHz) #define LPLL_HZ (816 * MHz) #define GPLL_HZ (1188 * MHz) #define CPLL_HZ (1500 * MHz) #define NPLL_HZ (850 * MHz) #define PPLL_HZ (1100 * MHz) +#define SPLL_HZ (702 * MHz) /* RK3588 pll id */ enum rk3588_pll_id { @@ -447,5 +447,22 @@ enum { CLK_I2C0_SEL_MASK = 1 << CLK_I2C0_SEL_SHIFT, CLK_I2C_SEL_200M = 0, CLK_I2C_SEL_100M, + + /* SECURECRU_CLKSEL_CON01 */ + SCMI_HCLK_SD_SEL_SHIFT = 2, + SCMI_HCLK_SD_SEL_MASK = 3 << SCMI_HCLK_SD_SEL_SHIFT, + SCMI_HCLK_SD_SEL_150M = 0, + SCMI_HCLK_SD_SEL_100M, + SCMI_HCLK_SD_SEL_50M, + SCMI_HCLK_SD_SEL_24M, + + /* SECURECRU_CLKSEL_CON03 */ + SCMI_CCLK_SD_SEL_SHIFT = 12, + SCMI_CCLK_SD_SEL_MASK = 3 << SCMI_CCLK_SD_SEL_SHIFT, + SCMI_CCLK_SD_SEL_GPLL = 0, + SCMI_CCLK_SD_SEL_SPLL, + SCMI_CCLK_SD_SEL_24M, + SCMI_CCLK_SD_DIV_SHIFT = 6, + SCMI_CCLK_SD_DIV_MASK = 0x3f << SCMI_CCLK_SD_DIV_SHIFT, }; #endif |