Revert most of the series for adding vexpress_aemv8r support

Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list.  We should keep the first patch in the
series for now, but revert the rest.  This reverts the following
commits:

e0bd6f31ce41 doc: Add documentation for the Arm vexpress board configs
30e5a449e8c7 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca63bf4 vexpress64: Add BASER_FVP vexpress board variant
2f5b7b74903f armv8: Add ARMv8 MPU configuration logic
37a757e227cc armv8: Ensure EL1&0 VMSA is enabled

Signed-off-by: Tom Rini <trini@konsulko.com>

3 files changed, 0 insertions, 102 deletions

diff --git a/arch/arm/include/asm/armv8/mpu.h b/arch/arm/include/asm/armv8/mpu.h
deleted file mode 100644
index c6c8828325..0000000000
--- a/arch/arm/include/asm/armv8/mpu.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- *
- * (C) Copyright 2021 Arm Limited
- */
-
-#ifndef _ASM_ARMV8_MPU_H_
-#define _ASM_ARMV8_MPU_H_
-
-#include <asm/armv8/mmu.h>
-#include <asm/barriers.h>
-#include <linux/stringify.h>
-
-#define PRSELR_EL2		S3_4_c6_c2_1
-#define PRBAR_EL2		S3_4_c6_c8_0
-#define PRLAR_EL2		S3_4_c6_c8_1
-#define MPUIR_EL2		S3_4_c0_c0_4
-
-#define PRBAR_ADDRESS(addr)	((addr) & ~(0x3fULL))
-
-/* Access permissions */
-#define PRBAR_AP(val)		(((val) & 0x3) << 2)
-#define PRBAR_AP_RW_HYP		PRBAR_AP(0x0)
-#define PRBAR_AP_RW_ANY		PRBAR_AP(0x1)
-#define PRBAR_AP_RO_HYP		PRBAR_AP(0x2)
-#define PRBAR_AP_RO_ANY		PRBAR_AP(0x3)
-
-/* Shareability */
-#define PRBAR_SH(val)		(((val) & 0x3) << 4)
-#define PRBAR_NON_SH		PRBAR_SH(0x0)
-#define PRBAR_OUTER_SH		PRBAR_SH(0x2)
-#define PRBAR_INNER_SH		PRBAR_SH(0x3)
-
-/* Memory attribute (MAIR idx) */
-#define PRLAR_ATTRIDX(val)	(((val) & 0x7) << 1)
-#define PRLAR_EN_BIT		(0x1)
-#define PRLAR_ADDRESS(addr)	((addr) & ~(0x3fULL))
-
-#ifndef __ASSEMBLY__
-
-static inline void setup_el2_mpu_region(uint8_t region, uint64_t base, uint64_t limit)
-{
-	asm volatile("msr " __stringify(PRSELR_EL2) ", %0" : : "r" (region));
-	isb();
-	asm volatile("msr " __stringify(PRBAR_EL2) ", %0" : : "r" (base));
-	asm volatile("msr " __stringify(PRLAR_EL2) ", %0" : : "r" (limit));
-	dsb();
-	isb();
-}
-
-#endif
-
-struct mpu_region {
-	u64 start;
-	u64 end;
-	u64 attrs;
-};
-
-extern struct mpu_region *mpu_mem_map;
-
-#endif /* _ASM_ARMV8_MPU_H_ */
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index ecd8221c0d..e1eefc283f 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -316,23 +316,6 @@ lr	.req	x30
 	csel	\tmp, \tmp2, \tmp, eq
 	msr	hcr_el2, \tmp
 
-	/*
-	 * Detect whether the system has a configurable memory system
-	 * architecture at EL1&0
-	 */
-	mrs	\tmp, id_aa64mmfr0_el1
-	lsr	\tmp, \tmp, #48
-	and	\tmp, \tmp, #((ID_AA64MMFR0_EL1_MSA_MASK | \
-			ID_AA64MMFR0_EL1_MSA_FRAC_MASK) >> 48)
-	cmp	\tmp, #((ID_AA64MMFR0_EL1_MSA_USE_FRAC | \
-			ID_AA64MMFR0_EL1_MSA_FRAC_VMSA) >> 48)
-	bne	2f
-
-	/* Ensure the EL1&0 VMSA is enabled */
-	mov	\tmp, #(VTCR_EL2_MSA)
-	msr	vtcr_el2, \tmp
-2:
-
 	/* Return to the EL1_SP1 mode from EL2 */
 	ldr	\tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
 			SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1ec6237320..f75eea16b3 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -84,30 +84,6 @@
 #define HCR_EL2_HCD_DIS		(1 << 29) /* Hypervisor Call disabled         */
 
 /*
- * VTCR_EL2 bits definitions
- */
-#define VTCR_EL2_MSA      	(1 << 31) /* EL1&0 memory architecture        */
-
-/*
- * ID_AA64MMFR0_EL1 bits definitions
- */
-#define ID_AA64MMFR0_EL1_MSA_FRAC_MASK		(0xFUL << 52) /* Memory system
-								 architecture
-								 frac         */
-#define ID_AA64MMFR0_EL1_MSA_FRAC_VMSA		(0x2UL << 52) /* EL1&0 supports
-								 VMSA         */
-#define ID_AA64MMFR0_EL1_MSA_FRAC_PMSA		(0x1UL << 52) /* EL1&0 only
-							         supports PMSA*/
-#define ID_AA64MMFR0_EL1_MSA_FRAC_NO_PMSA	(0x0UL << 52) /* No PMSA
-								 support      */
-#define ID_AA64MMFR0_EL1_MSA_MASK		(0xFUL << 48) /* Memory system
-								 architecture */
-#define ID_AA64MMFR0_EL1_MSA_USE_FRAC		(0xFUL << 48) /* Use MSA_FRAC */
-#define ID_AA64MMFR0_EL1_MSA_VMSA		(0x0UL << 48) /* Memory system
-								 architecture
-								 is VMSA      */
-
-/*
  * ID_AA64ISAR1_EL1 bits definitions
  */
 #define ID_AA64ISAR1_EL1_GPI	(0xF << 28) /* Implementation-defined generic