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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2018-11-15 08:34:50 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-11-27 06:52:11 +0300 |
| commit | ccdb7c2255bde555bd0d4e104f8d228e25b76572 (patch) | |
| tree | 0729f8f35361062cc31ec767dc5f7852c63a6396 /arch/arm/mach-k3/Makefile | |
| parent | f7bb20a53e829ce0b4d3c22c704e80b490d24016 (diff) | |
| download | u-boot-ccdb7c2255bde555bd0d4e104f8d228e25b76572.tar.xz | |
armv7r: K3: Allow SPL to run only on core 0
Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.
If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.
If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-k3/Makefile')
| -rw-r--r-- | arch/arm/mach-k3/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 406dda3b02..bd4ab361b2 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -5,5 +5,5 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o -obj-$(CONFIG_CPU_V7R) += r5_mpu.o +obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o obj-y += common.o |