diff options
| author | Bhavya Kapoor <b-kapoor@ti.com> | 2023-05-12 13:02:53 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-06-01 19:40:16 +0300 |
| commit | 414cad08cb7bd3814aad7e800f861d5bffad0fd2 (patch) | |
| tree | 7f31e193fa5c2c43159f99107f901ff3f96145a6 /arch/arm/mach-k3 | |
| parent | f8504792e830348669479cb1eeee0c0c3877debf (diff) | |
| download | u-boot-414cad08cb7bd3814aad7e800f861d5bffad0fd2.tar.xz | |
arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock data
Add main_uart1 clocks in clk-data.c for J7200. Now,
main_uart1 clocks will be set up while booting the J7200 SoC.
Signed-off-by: Bhavya Kapoor <b-kapoor@ti.com>
Diffstat (limited to 'arch/arm/mach-k3')
| -rw-r--r-- | arch/arm/mach-k3/j7200/clk-data.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 0437e30abb..9b45786a2d 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), @@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), + DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 108, + .clk_list_cnt = 109, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 127, + .soc_dev_clk_data_cnt = 129, }; |