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author | Trevor Woerner <twoerner@gmail.com> | 2020-05-06 15:02:36 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2020-05-15 21:47:35 +0300 |
commit | b3d9a8b1857878fd72bf5385d91585fbafe516d6 (patch) | |
tree | fd11b9f6b343aabb33247b4b3fe4ccfde1cc8a6f /arch/arm/mach-lpc32xx/timer.c | |
parent | 0ff042d836f2a40b2104d4501111fbb340293c5c (diff) | |
download | u-boot-b3d9a8b1857878fd72bf5385d91585fbafe516d6.tar.xz |
arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.
Following the checklist from
commit 01f14456306c ("ARM: prepare for moving SoC sources into mach-*"):
[1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
[2] add machine entry to arch/arm/Makefile
[3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
[4] fix the Kconfig file path in arch/arm/Kconfig
[5] (no MAINTAINERS update)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Diffstat (limited to 'arch/arm/mach-lpc32xx/timer.c')
-rw-r--r-- | arch/arm/mach-lpc32xx/timer.c | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c new file mode 100644 index 0000000000..3a896d10ca --- /dev/null +++ b/arch/arm/mach-lpc32xx/timer.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com> + */ + +#include <common.h> +#include <time.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/timer.h> +#include <asm/io.h> + +static struct timer_regs *timer0 = (struct timer_regs *)TIMER0_BASE; +static struct timer_regs *timer1 = (struct timer_regs *)TIMER1_BASE; +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; + +static void lpc32xx_timer_clock(u32 bit, int enable) +{ + if (enable) + setbits_le32(&clk->timclk_ctrl1, bit); + else + clrbits_le32(&clk->timclk_ctrl1, bit); +} + +static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq) +{ + writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); + writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); + writel(0, &timer->tc); + writel(0, &timer->pr); + + /* Count mode is every rising PCLK edge */ + writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr); + + /* Set prescale counter value */ + writel((get_periph_clk_rate() / freq) - 1, &timer->pr); + + /* Ensure that the counter is not reset when matching TC */ + writel(0, &timer->mcr); +} + +static void lpc32xx_timer_count(struct timer_regs *timer, int enable) +{ + if (enable) + writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); + else + writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); +} + +int timer_init(void) +{ + lpc32xx_timer_clock(CLK_TIMCLK_TIMER0, 1); + lpc32xx_timer_reset(timer0, CONFIG_SYS_HZ); + lpc32xx_timer_count(timer0, 1); + + return 0; +} + +ulong get_timer(ulong base) +{ + return readl(&timer0->tc) - base; +} + +void __udelay(unsigned long usec) +{ + lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 1); + lpc32xx_timer_reset(timer1, CONFIG_SYS_HZ * 1000); + lpc32xx_timer_count(timer1, 1); + + while (readl(&timer1->tc) < usec) + /* NOP */; + + lpc32xx_timer_count(timer1, 0); + lpc32xx_timer_clock(CLK_TIMCLK_TIMER1, 0); +} + +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} |