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authorLey Foon Tan <ley.foon.tan@intel.com>2017-04-25 21:44:48 +0300
committerMarek Vasut <marex@denx.de>2017-05-18 12:33:19 +0300
commitd89e979c42892db572c4ef5d56bc207075953f58 (patch)
tree497806ec47a6c1bf620303829cdb095374e55f76 /arch/arm/mach-socfpga/Makefile
parent9b21de78116ccb4c47dc82daae9598e19060f669 (diff)
downloadu-boot-d89e979c42892db572c4ef5d56bc207075953f58.tar.xz
arm: socfpga: Enable build for Arria 10
Update Kconfig and Makefile to enable Arria 10. Clean up Makefile and sorting *.o alphanumerically. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'arch/arm/mach-socfpga/Makefile')
-rw-r--r--arch/arm/mach-socfpga/Makefile46
1 files changed, 33 insertions, 13 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 4ce8eaca6c..41b779c5ca 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,28 +2,48 @@
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
-# Copyright (C) 2012 Altera Corporation <www.altera.com>
+# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += misc.o timer.o reset_manager.o clock_manager.o \
- fpga_manager.o board.o
+obj-y += board.o
+obj-y += clock_manager.o
+obj-y += fpga_manager.o
+obj-y += misc.o
+obj-y += reset_manager.o
+obj-y += timer.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
- pinmux_arria10.o \
- misc_arria10.o \
- reset_manager_arria10.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y += clock_manager_gen5.o
+obj-y += misc_gen5.o
+obj-y += reset_manager_gen5.o
+obj-y += scan_manager.o
+obj-y += system_manager_gen5.o
+obj-y += wrap_pll_config.o
+endif
-obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+obj-y += clock_manager_arria10.o
+obj-y += misc_arria10.o
+obj-y += pinmux_arria10.o
+obj-y += reset_manager_arria10.o
+endif
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
+obj-y += freeze_controller.o
+obj-y += wrap_iocsr_config.o
+obj-y += wrap_pinmux_config.o
+obj-y += wrap_sdram_config.o
+endif
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
# QTS-generated config file wrappers
-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
- clock_manager_gen5.o reset_manager_gen5.o \
- misc_gen5.o system_manager_gen5.o
-obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
- wrap_sdram_config.o
CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
+endif