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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-08 05:38:19 +0300
committerMarek Vasut <marex@denx.de>2020-01-07 16:38:33 +0300
commitbb25aca1343304e0334e9eebfb9d350eaf276882 (patch)
tree00e8e1c3b79e4a6175bfeccf716d106ec02593cc /arch/arm/mach-socfpga/misc.c
parentdd72cbd9e91dfa80f04a5921546d19e189bb2361 (diff)
downloadu-boot-bb25aca1343304e0334e9eebfb9d350eaf276882.tar.xz
arm: socfpga: Convert reset manager from struct to defines
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
-rw-r--r--arch/arm/mach-socfpga/misc.c41
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 904b3d030a..3f3ff8e23b 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,6 +23,8 @@
DECLARE_GLOBAL_DATA_PTR;
+phys_addr_t socfpga_rstmgr_base __section(".data");
+
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -146,6 +148,8 @@ void socfpga_fpga_add(void *fpga_desc)
int arch_cpu_init(void)
{
+ socfpga_get_managers_addr();
+
#ifdef CONFIG_HW_WATCHDOG
/*
* In case the watchdog is enabled, make sure to (re-)configure it
@@ -203,3 +207,40 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
);
#endif
+
+static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
+{
+ const void *blob = gd->fdt_blob;
+ struct fdt_resource r;
+ int node;
+ int ret;
+
+ node = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (node < 0)
+ return node;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ return -ENODEV;
+
+ ret = fdt_get_resource(blob, node, "reg", 0, &r);
+ if (ret)
+ return ret;
+
+ *base = (phys_addr_t)r.start;
+
+ return 0;
+}
+
+void socfpga_get_managers_addr(void)
+{
+ int ret;
+
+ ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
+ if (ret)
+ hang();
+}
+
+phys_addr_t socfpga_get_rstmgr_addr(void)
+{
+ return socfpga_rstmgr_base;
+}