diff options
| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-09-04 13:55:19 +0300 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-10-21 19:12:20 +0300 |
| commit | 67f9f11f197ff39e4e85e56bca84206ef18ab296 (patch) | |
| tree | 07de292e9c7270f10fe067390c8d251de2d92c39 /arch/arm/mach-stm32mp/cpu.c | |
| parent | c981d67a0444cf31e5a16fe4be79d785eb182385 (diff) | |
| download | u-boot-67f9f11f197ff39e4e85e56bca84206ef18ab296.tar.xz | |
stm32mp: limit size of cacheable DDR in pre-reloc stage
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.
This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
Without security, in basic boot, the value is equal to STM32_DDR_SIZE.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cpu.c')
| -rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index f19e5c3f33..6785ab6b58 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -230,7 +230,8 @@ static void early_enable_caches(void) round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, DCACHE_DEFAULT_OPTION); } |