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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-11-04 11:22:09 +0300 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-11-25 12:33:16 +0300 |
| commit | 77c077e1713d4f45c3e2972ab487b6f6f2bbabc0 (patch) | |
| tree | 383e1829aaaaaf9f2b94c82a90a5f2405458889a /arch/arm/mach-stm32mp/cpu.c | |
| parent | d5b05113912989f2f23f0bb130bce7e42a9cacd1 (diff) | |
| download | u-boot-77c077e1713d4f45c3e2972ab487b6f6f2bbabc0.tar.xz | |
arm: stm32mp: correct the ALIGN macro usage
Correct the ALIGN macro usage in mmu_set_region_dcache_behaviour
call: the address must use ALIGN_DOWN and size can use ALIGN macro.
With STM32_SYSRAM_BASE=0x2FFC0000 and MMU_SECTION_SIZE=0x100000 for
STM32MP15x the computed address was 30000000 instead of 2ff00000.
Fixes: 43fe9d2fda24 ("stm32mp1: mmu_set_region_dcache_behaviour")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/cpu.c')
| -rw-r--r-- | arch/arm/mach-stm32mp/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 6785ab6b58..1520c6eaed 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -226,8 +226,8 @@ static void early_enable_caches(void) if (IS_ENABLED(CONFIG_SPL_BUILD)) mmu_set_region_dcache_behaviour( - ALIGN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), - round_up(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), + ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE), + ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE), DCACHE_DEFAULT_OPTION); else mmu_set_region_dcache_behaviour(STM32_DDR_BASE, |