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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-02-01 11:53:01 +0300 |
|---|---|---|
| committer | Tom <twarren@nvidia.com> | 2023-02-02 20:16:41 +0300 |
| commit | 87a758652b4f6d343f19d23bd5dba7d0f2491245 (patch) | |
| tree | 04771d501ddfb1100ab0352138ee0cbdd4902241 /arch/arm/mach-tegra/clock.c | |
| parent | 1e1cd8eb2d0c8e5b28b2dd6622ec9cbbd5eb61b8 (diff) | |
| download | u-boot-87a758652b4f6d343f19d23bd5dba7d0f2491245.tar.xz | |
ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20.
This patch remaps it to use additional frequencies, added in
T30+ SoC while maintaining backwards compatibility with T20.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20
Tested-by: Thierry Reding <treding@nvidia.com> # T30, T124, T210
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/clock.c')
| -rw-r--r-- | arch/arm/mach-tegra/clock.c | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 77c8ad978e..11bffc1701 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -28,16 +28,23 @@ static unsigned pll_rate[CLOCK_ID_COUNT]; /* - * The oscillator frequency is fixed to one of four set values. Based on this + * The oscillator frequency is fixed to one of seven set values. Based on this * the other clocks are set up appropriately. */ static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = { 13000000, + 16800000, + 0, + 0, 19200000, - 12000000, - 26000000, 38400000, + 0, + 0, + 12000000, 48000000, + 0, + 0, + 26000000, }; /* return 1 if a peripheral ID is in range */ @@ -766,6 +773,7 @@ void tegra30_set_up_pllp(void) */ switch (clock_get_osc_freq()) { case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */ + case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */ clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8); break; @@ -776,10 +784,13 @@ void tegra30_set_up_pllp(void) break; case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */ + case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */ clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8); clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8); break; + case CLOCK_OSC_FREQ_19_2: + case CLOCK_OSC_FREQ_38_4: default: /* * These are not supported. It is too early to print a |