diff options
| author | Peng Fan <peng.fan@nxp.com> | 2020-12-27 04:37:06 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-01-23 13:30:30 +0300 |
| commit | 50d09531274211436d0d5038d4eefc8be12c0726 (patch) | |
| tree | c109352cf75c04003b8bc4a14803e958f2ce39a3 /arch/arm | |
| parent | 6489dac3ab1e6d50c6847f017e839fcc1deb0c40 (diff) | |
| download | u-boot-50d09531274211436d0d5038d4eefc8be12c0726.tar.xz | |
arm: dts: imx8mn: sync dts from Linux Kernel
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/dts/imx8mn-ddr4-evk.dts | 321 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mn-evk.dtsi | 360 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mn-pinfunc.h | 1266 | ||||
| -rw-r--r-- | arch/arm/dts/imx8mn.dtsi | 411 |
4 files changed, 1474 insertions, 884 deletions
diff --git a/arch/arm/dts/imx8mn-ddr4-evk.dts b/arch/arm/dts/imx8mn-ddr4-evk.dts index 9b2c1727a8..7dfee715a2 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk.dts +++ b/arch/arm/dts/imx8mn-ddr4-evk.dts @@ -6,216 +6,151 @@ /dts-v1/; #include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" / { model = "NXP i.MX8MNano DDR4 EVK board"; compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; - - chosen { - stdout-path = &uart2; - }; - - reg_usdhc2_vmmc: regulator-usdhc2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; }; -&iomuxc { - pinctrl-names = "default"; - - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; - - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { - fsl,pins = < - MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 - >; - }; +&A53_0 { + cpu-supply = <&buck2_reg>; +}; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 - >; - }; +&A53_1 { + cpu-supply = <&buck2_reg>; +}; - pinctrl_usdhc2_gpio: usdhc2grpgpio { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 - >; - }; +&A53_2 { + cpu-supply = <&buck2_reg>; +}; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; +&A53_3 { + cpu-supply = <&buck2_reg>; +}; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 - >; - }; + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp100mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; - pinctrl_usdhc3_200mhz: usdhc3grp200mhz { - fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; + opp-600M { + opp-hz = /bits/ 64 <600000000>; + }; }; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - at803x,led-act-blind-workaround; - at803x,eee-disabled; - at803x,vddio-1p8v; +&i2c1 { + pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "buck4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "buck5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "buck6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; }; }; - -&snvs_pwrkey { - status = "okay"; -}; - -&uart2 { /* console */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - status = "okay"; -}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi new file mode 100644 index 0000000000..76d042a4cf --- /dev/null +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +#include <dt-bindings/usb/pd.h> +#include "imx8mn.dtsi" + +/ { + chosen { + stdout-path = &uart2; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "yellow:status"; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + linux,autosuspend-period = <125>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec1>; + reg = <0x50>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) + PDO_VAR(5000, 20000, 3000)>; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + >; + }; + + pinctrl_ir: irgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_typec1: typec1grp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + >; + }; +}; diff --git a/arch/arm/dts/imx8mn-pinfunc.h b/arch/arm/dts/imx8mn-pinfunc.h index 3de8168cf8..faf1e69e74 100644 --- a/arch/arm/dts/imx8mn-pinfunc.h +++ b/arch/arm/dts/imx8mn-pinfunc.h @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP - * + * Copyright 2018-2019 NXP */ #ifndef __DTS_IMX8MN_PINFUNC_H @@ -11,636 +10,637 @@ * The pin function ID is a tuple of * <mux_reg conf_reg input_reg mux_mode input_val> */ -#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x0020 0x025C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x0020 0x025C 0x055C 0x1 0x3 -#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x0024 0x0260 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x0024 0x0260 0x056C 0x1 0x3 -#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0028 0x0290 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x0028 0x0290 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0028 0x0290 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x0028 0x0290 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x002C 0x0294 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x002C 0x0294 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x002C 0x0294 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x002C 0x0294 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x0030 0x0298 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x0030 0x0298 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x0030 0x0298 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x0034 0x029C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x0034 0x029C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x0034 0x029C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x0034 0x029C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0038 0x02A0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0038 0x02A0 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x0038 0x02A0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x0038 0x02A0 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x003C 0x02A4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x003C 0x02A4 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x003C 0x02A4 0x04BC 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x003C 0x02A4 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0040 0x02A8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x0040 0x02A8 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x0040 0x02A8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x0040 0x02A8 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0044 0x02AC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x0044 0x02AC 0x04C0 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x0044 0x02AC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x0044 0x02AC 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0048 0x02B0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x0048 0x02B0 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x0048 0x02B0 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x0048 0x02B0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x0048 0x02B0 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x004C 0x02B4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x004C 0x02B4 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x004C 0x02B4 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x004C 0x02B4 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x004C 0x02B4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x004C 0x02B4 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0050 0x02B8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x0050 0x02B8 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x0050 0x02B8 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x0054 0x02BC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x0054 0x02BC 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x0054 0x02BC 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x0054 0x02BC 0x04BC 0x5 0x1 -#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x0054 0x02BC 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x0058 0x02C0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x0058 0x02C0 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x0058 0x02C0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x0058 0x02C0 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x005C 0x02C4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x005C 0x02C4 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x005C 0x02C4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x005C 0x02C4 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0060 0x02C8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x0060 0x02C8 0x0598 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x0060 0x02C8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x0060 0x02C8 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0064 0x02CC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x0064 0x02CC 0x05B8 0x4 0x2 -#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x0064 0x02CC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x0064 0x02CC 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x0068 0x02D0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x0068 0x02D0 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x0068 0x02D0 0x0540 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x0068 0x02D0 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x0068 0x02D0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x0068 0x02D0 0x059C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x006C 0x02D4 0x04C0 0x0 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x006C 0x02D4 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x006C 0x02D4 0x053C 0x3 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x006C 0x02D4 0x05CC 0x4 0x1 -#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x006C 0x02D4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x006C 0x02D4 0x0550 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x0070 0x02D8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x0070 0x02D8 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x0070 0x02D8 0x0538 0x3 0x1 -#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x0070 0x02D8 0x0568 0x4 0x1 -#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x0070 0x02D8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x0070 0x02D8 0x0584 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x0074 0x02DC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x0074 0x02DC 0x05A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0074 0x02DC 0x05A4 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x0074 0x02DC 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x0074 0x02DC 0x0540 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x0074 0x02DC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x0074 0x02DC 0x054C 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x0078 0x02E0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x0078 0x02E0 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x0078 0x02E0 0x053C 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x0078 0x02E0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x0078 0x02E0 0x0598 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x007C 0x02E4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x007C 0x02E4 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x007C 0x02E4 0x0538 0x3 0x2 -#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x007C 0x02E4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x007C 0x02E4 0x05B8 0x6 0x3 -#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x0080 0x02E8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x0080 0x02E8 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x0080 0x02E8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x0080 0x02E8 0x05B4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0084 0x02EC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x0084 0x02EC 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x0084 0x02EC 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x0084 0x02EC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x0084 0x02EC 0x05B0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x0088 0x02F0 0x0574 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x0088 0x02F0 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x0088 0x02F0 0x0540 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x0088 0x02F0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x0088 0x02F0 0x05E4 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x008C 0x02F4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x008C 0x02F4 0x05C8 0x1 0x0 -#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x008C 0x02F4 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x008C 0x02F4 0x053C 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x008C 0x02F4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x008C 0x02F4 0x05E0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x0090 0x02F8 0x057C 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x0090 0x02F8 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x0090 0x02F8 0x0538 0x3 0x3 -#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x0090 0x02F8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x0090 0x02F8 0x0558 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x0094 0x02FC 0x0554 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x0094 0x02FC 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x0094 0x02FC 0x0534 0x3 0x1 -#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x0094 0x02FC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x0094 0x02FC 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x0098 0x0300 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x0098 0x0300 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x0098 0x0300 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x0098 0x0300 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x0098 0x0300 0x05A0 0x6 0x1 -#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x009C 0x0304 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x009C 0x0304 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x009C 0x0304 0x05CC 0x3 0x5 -#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x009C 0x0304 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x009C 0x0304 0x05DC 0x6 0x1 -#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x00A0 0x0308 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x00A0 0x0308 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x00A0 0x0308 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x00A0 0x0308 0x04F4 0x4 0x4 -#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x00A0 0x0308 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x00A4 0x030C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x00A4 0x030C 0x04C0 0x1 0x3 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x00A4 0x030C 0x04F4 0x4 0x5 -#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x00A4 0x030C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x00A4 0x030C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x00A8 0x0310 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x00A8 0x0310 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x00A8 0x0310 0x04F0 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x00A8 0x0310 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x00A8 0x0310 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x00AC 0x0314 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x00AC 0x0314 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x00AC 0x0314 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x00AC 0x0314 0x04F0 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x00AC 0x0314 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x00B0 0x0318 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x00B0 0x0318 0x057C 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x00B0 0x0318 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x00B0 0x0318 0x04FC 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x00B0 0x0318 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x00B4 0x031C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x00B4 0x031C 0x0554 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x00B4 0x031C 0x04FC 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x00B4 0x031C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x00B4 0x031C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x00B8 0x0320 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x00B8 0x0320 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x00B8 0x0320 0x055C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x00B8 0x0320 0x04F8 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x00B8 0x0320 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00B8 0x0320 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x00BC 0x0324 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x00BC 0x0324 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x00BC 0x0324 0x056C 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x00BC 0x0324 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x00BC 0x0324 0x04F8 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00BC 0x0324 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x00C0 0x0328 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x00C0 0x0328 0x0574 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x00C0 0x0328 0x05D0 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x00C0 0x0328 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x00C0 0x0328 0x0504 0x4 0x4 -#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00C0 0x0328 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x00C4 0x032C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x00C4 0x032C 0x05C8 0x1 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x00C4 0x032C 0x0560 0x3 0x1 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x00C4 0x032C 0x0504 0x4 0x5 -#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x00C4 0x032C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00C4 0x032C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x00C8 0x0330 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x00C8 0x0330 0x05A4 0x1 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x00C8 0x0330 0x05A4 0x1 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x00C8 0x0330 0x0588 0x3 0x1 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x00C8 0x0330 0x0500 0x4 0x2 -#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x00C8 0x0330 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x00C8 0x0330 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x00CC 0x0334 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x00CC 0x0334 0x05BC 0x3 0x1 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x00CC 0x0334 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x00CC 0x0334 0x0500 0x4 0x3 -#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x00CC 0x0334 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x00D0 0x0338 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x00D0 0x0338 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x00D0 0x0338 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x00D4 0x033C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x00D4 0x033C 0x04E4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x00D4 0x033C 0x0580 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x00D4 0x033C 0x050C 0x3 0x4 -#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x00D4 0x033C 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x00D4 0x033C 0x0594 0x4 0x1 -#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x00D4 0x033C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x00D4 0x033C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x00D8 0x0340 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x00D8 0x0340 0x04D0 0x1 0x1 -#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x00D8 0x0340 0x0590 0x2 0x1 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x00D8 0x0340 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x00D8 0x0340 0x050C 0x3 0x5 -#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x00D8 0x0340 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x00D8 0x0340 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x00D8 0x0340 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x00DC 0x0344 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x00DC 0x0344 0x04D4 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x00DC 0x0344 0x058C 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x00DC 0x0344 0x04FC 0x3 0x6 -#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x00DC 0x0344 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x00DC 0x0344 0x0534 0x4 0x2 -#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x00DC 0x0344 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x00DC 0x0344 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x00E0 0x0348 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x00E0 0x0348 0x04EC 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x00E0 0x0348 0x05D4 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x00E0 0x0348 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x00E0 0x0348 0x04FC 0x3 0x7 -#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x00E0 0x0348 0x0538 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x00E0 0x0348 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x00E0 0x0348 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x00E4 0x034C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x00E4 0x034C 0x04E8 0x1 0x1 -#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x00E4 0x034C 0x0570 0x2 0x2 -#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x00E4 0x034C 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x00E4 0x034C 0x053C 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x00E4 0x034C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x00E4 0x034C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x00E8 0x0350 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x00E8 0x0350 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x00E8 0x0350 0x0578 0x2 0x1 -#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x00E8 0x0350 0x05CC 0x3 0x2 -#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x00E8 0x0350 0x0540 0x4 0x4 -#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x00E8 0x0350 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x00E8 0x0350 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x00EC 0x0354 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x00EC 0x0354 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x00EC 0x0354 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x00F0 0x0358 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x00F0 0x0358 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x00F0 0x0358 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00F4 0x035C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x00F4 0x035C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x00F4 0x035C 0x0534 0x3 0x3 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x00F4 0x035C 0x0504 0x4 0x6 -#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x00F4 0x035C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x00F4 0x035C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x00F4 0x035C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00F8 0x0360 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x00F8 0x0360 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x00F8 0x0360 0x0538 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x00F8 0x0360 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x00F8 0x0360 0x0504 0x4 0x7 -#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00F8 0x0360 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x00F8 0x0360 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00FC 0x0364 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x00FC 0x0364 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x00FC 0x0364 0x059C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x00FC 0x0364 0x0534 0x3 0x4 -#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x00FC 0x0364 0x05D4 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x00FC 0x0364 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x00FC 0x0364 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x0100 0x0368 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x0100 0x0368 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x0100 0x0368 0x0550 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x0100 0x0368 0x0538 0x3 0x6 -#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x0100 0x0368 0x058C 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x0100 0x0368 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x0100 0x0368 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x0104 0x036C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x0104 0x036C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x0104 0x036C 0x0584 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x0104 0x036C 0x053C 0x3 0x5 -#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x0104 0x036C 0x05BC 0x4 0x2 -#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x0104 0x036C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x0104 0x036C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x0108 0x0370 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x0108 0x0370 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x0108 0x0370 0x054C 0x2 0x0 -#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x0108 0x0370 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x0108 0x0370 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x010C 0x0374 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x010C 0x0374 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x010C 0x0374 0x053C 0x3 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x010C 0x0374 0x050C 0x4 0x6 -#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x010C 0x0374 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x010C 0x0374 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x010C 0x0374 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x0110 0x0378 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x0110 0x0378 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x0110 0x0378 0x0540 0x3 0x5 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x0110 0x0378 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x0110 0x0378 0x050C 0x4 0x7 -#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x0110 0x0378 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x0110 0x0378 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x0114 0x037C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x0114 0x037C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x0114 0x037C 0x0598 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x0114 0x037C 0x058C 0x4 0x3 -#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0114 0x037C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x0114 0x037C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x0118 0x0380 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x0118 0x0380 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x0118 0x0380 0x05B8 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0118 0x0380 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x0118 0x0380 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x011C 0x0384 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x011C 0x0384 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x011C 0x0384 0x05B4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x011C 0x0384 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x011C 0x0384 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x0120 0x0388 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x0120 0x0388 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x0120 0x0388 0x05B0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x0120 0x0388 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x0120 0x0388 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x0124 0x038C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x0124 0x038C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x0124 0x038C 0x05E4 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x0124 0x038C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x0124 0x038C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x0128 0x0390 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x0128 0x0390 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x0128 0x0390 0x05E0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x0128 0x0390 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x0128 0x0390 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x012C 0x0394 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x012C 0x0394 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x012C 0x0394 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x012C 0x0394 0x0588 0x4 0x2 -#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x012C 0x0394 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x012C 0x0394 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x0130 0x0398 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x0130 0x0398 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x0130 0x0398 0x0558 0x2 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x0130 0x0398 0x0538 0x3 0x7 -#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x0130 0x0398 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x0130 0x0398 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x0134 0x039C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x0134 0x039C 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x0134 0x039C 0x0540 0x3 0x6 -#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x0134 0x039C 0x0588 0x4 0x3 -#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x0134 0x039C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x0134 0x039C 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x0138 0x03A0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x0138 0x03A0 0x05A0 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x0138 0x03A0 0x05BC 0x4 0x3 -#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x0138 0x03A0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x0138 0x03A0 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x013C 0x03A4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x013C 0x03A4 0x05DC 0x2 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x013C 0x03A4 0x058C 0x4 0x4 -#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x013C 0x03A4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x013C 0x03A4 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x0140 0x03A8 0x04E4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0140 0x03A8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x0144 0x03AC 0x04D0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x0144 0x03AC 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x0144 0x03AC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0148 0x03B0 0x04D4 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x0148 0x03B0 0x0534 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x0148 0x03B0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x014C 0x03B4 0x04D8 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x014C 0x03B4 0x04EC 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x014C 0x03B4 0x0538 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x014C 0x03B4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x0150 0x03B8 0x04DC 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x0150 0x03B8 0x04E8 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x0150 0x03B8 0x053C 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x0150 0x03B8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x0154 0x03BC 0x04E0 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x0154 0x03BC 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x0154 0x03BC 0x0540 0x4 0x0 -#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x0154 0x03BC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x0158 0x03C0 0x0594 0x0 0x0 -#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0158 0x03C0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x01B0 0x0418 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x01B0 0x0418 0x04EC 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x01B0 0x0418 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x01B0 0x0418 0x05AC 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x01B0 0x0418 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x01B0 0x0418 0x04F4 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x01B0 0x0418 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x01B0 0x0418 0x053C 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x01B4 0x041C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x01B4 0x041C 0x04E8 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x01B4 0x041C 0x04F4 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x01B4 0x041C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x01B4 0x041C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x01B4 0x041C 0x0538 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x01B8 0x0420 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x01B8 0x0420 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x01B8 0x0420 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x01B8 0x0420 0x04F0 0x4 0x2 -#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x01B8 0x0420 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x01B8 0x0420 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x01B8 0x0420 0x0540 0x6 0x7 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x01BC 0x0424 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x01BC 0x0424 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x01BC 0x0424 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x01BC 0x0424 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x01BC 0x0424 0x04F0 0x4 0x3 -#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x01BC 0x0424 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x01BC 0x0424 0x053C 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x01C0 0x0428 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x01C0 0x0428 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x01C0 0x0428 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x01C0 0x0428 0x0538 0x6 0x9 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x01C4 0x042C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x01C4 0x042C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x01C4 0x042C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x01C4 0x042C 0x0540 0x6 0x8 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x01C8 0x0430 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x01C8 0x0430 0x0594 0x1 0x2 -#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x01C8 0x0430 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x01C8 0x0430 0x05C0 0x6 0x1 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x01CC 0x0434 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x01CC 0x0434 0x05F0 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x01CC 0x0434 0x04E4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x01CC 0x0434 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x01CC 0x0434 0x05CC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x01CC 0x0434 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x01CC 0x0434 0x0534 0x6 0x5 -#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x01D0 0x0438 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x01D0 0x0438 0x05E8 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x01D0 0x0438 0x04D0 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x01D0 0x0438 0x05AC 0x3 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x01D0 0x0438 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x01D0 0x0438 0x04F8 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x01D0 0x0438 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x01D0 0x0438 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x01D4 0x043C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x01D4 0x043C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x01D4 0x043C 0x04D4 0x2 0x2 -#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x01D4 0x043C 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x01D4 0x043C 0x04F8 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x01D4 0x043C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x01D4 0x043C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x01D4 0x043C 0x0538 0x6 0x10 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x01D8 0x0440 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x01D8 0x0440 0x05EC 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x01D8 0x0440 0x04D8 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x01D8 0x0440 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x01D8 0x0440 0x04FC 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x01D8 0x0440 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x01D8 0x0440 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x01D8 0x0440 0x0540 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x01DC 0x0444 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x01DC 0x0444 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x01DC 0x0444 0x04DC 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x01DC 0x0444 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x01DC 0x0444 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x01DC 0x0444 0x04FC 0x4 0x3 -#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x01DC 0x0444 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x01DC 0x0444 0x053C 0x6 0x9 -#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x01E0 0x0448 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x01E0 0x0448 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x01E0 0x0448 0x04E0 0x2 0x1 -#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x01E0 0x0448 0x0568 0x4 0x2 -#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x01E0 0x0448 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x01E0 0x0448 0x0000 0x6 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x01E4 0x044C 0x05C0 0x0 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x01E4 0x044C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x01E4 0x044C 0x0594 0x2 0x3 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x01E4 0x044C 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x01E4 0x044C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x01E4 0x044C 0x05CC 0x6 0x4 -#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x01E8 0x0450 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x01E8 0x0450 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x01E8 0x0450 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x01EC 0x0454 0x05CC 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x01EC 0x0454 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x01EC 0x0454 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x01F0 0x0458 0x0568 0x0 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x01F0 0x0458 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x01F0 0x0458 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x01F4 0x045C 0x05D8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x01F4 0x045C 0x0504 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x01F4 0x045C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x01F4 0x045C 0x055C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x01F4 0x045C 0x04DC 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x01F4 0x045C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x01F8 0x0460 0x05A8 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x01F8 0x0460 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x01F8 0x0460 0x0504 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x01F8 0x0460 0x056C 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x01F8 0x0460 0x04D0 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x01F8 0x0460 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x01FC 0x0464 0x05C4 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x01FC 0x0464 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x01FC 0x0464 0x0500 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x01FC 0x0464 0x05D0 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x01FC 0x0464 0x04D4 0x3 0x3 -#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x01FC 0x0464 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x0200 0x0468 0x0564 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x0200 0x0468 0x0500 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x0200 0x0468 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x0200 0x0468 0x0560 0x2 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x0200 0x0468 0x04D8 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x0200 0x0468 0x04EC 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0200 0x0468 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0204 0x046C 0x0580 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x0204 0x046C 0x050C 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x0204 0x046C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x0204 0x046C 0x0588 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x0204 0x046C 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x0204 0x046C 0x04E8 0x4 0x3 -#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x0204 0x046C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0208 0x0470 0x0590 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x0208 0x0470 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x0208 0x0470 0x050C 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x0208 0x0470 0x05BC 0x2 0x4 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x0208 0x0470 0x04E0 0x3 0x2 -#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x0208 0x0470 0x0000 0x4 0x0 -#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x0208 0x0470 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x020C 0x0474 0x0578 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x020C 0x0474 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x020C 0x0474 0x0508 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x020C 0x0474 0x05D4 0x2 0x3 -#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x020C 0x0474 0x0594 0x3 0x4 -#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x020C 0x0474 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x0210 0x0478 0x0570 0x0 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x0210 0x0478 0x0508 0x1 0x1 -#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x0210 0x0478 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x0210 0x0478 0x058C 0x2 0x5 -#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0210 0x0478 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x0214 0x047C 0x055C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x0214 0x047C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x0214 0x047C 0x05D8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x0214 0x047C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x0218 0x0480 0x056C 0x0 0x0 -#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x0218 0x0480 0x04C0 0x1 0x2 -#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x0218 0x0480 0x05A8 0x3 0x1 -#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x0218 0x0480 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x021C 0x0484 0x05D0 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x021C 0x0484 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x021C 0x0484 0x0598 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x021C 0x0484 0x05C4 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x021C 0x0484 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x0220 0x0488 0x0560 0x0 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x0220 0x0488 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x0220 0x0488 0x05B8 0x2 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x0220 0x0488 0x0564 0x3 0x1 -#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x0220 0x0488 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x0224 0x048C 0x0588 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x0224 0x048C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x0224 0x048C 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x0224 0x048C 0x0580 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x0224 0x048C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x0228 0x0490 0x05BC 0x0 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x0228 0x0490 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x0228 0x0490 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x0228 0x0490 0x0590 0x3 0x2 -#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x0228 0x0490 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x022C 0x0494 0x05D4 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x022C 0x0494 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x022C 0x0494 0x0578 0x3 0x2 -#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x022C 0x0494 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x0230 0x0498 0x058C 0x0 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x0230 0x0498 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x0230 0x0498 0x0570 0x3 0x1 -#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x0230 0x0498 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x0234 0x049C 0x04F4 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x0234 0x049C 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x0234 0x049C 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x0234 0x049C 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x0238 0x04A0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x0238 0x04A0 0x04F4 0x0 0x1 -#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x0238 0x04A0 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x0238 0x04A0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x023C 0x04A4 0x04FC 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x023C 0x04A4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x023C 0x04A4 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x023C 0x04A4 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x023C 0x04A4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x0240 0x04A8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x0240 0x04A8 0x04FC 0x0 0x1 -#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x0240 0x04A8 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x0240 0x04A8 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x0240 0x04A8 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x0244 0x04AC 0x0504 0x0 0x2 -#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x0244 0x04AC 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x0244 0x04AC 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x0244 0x04AC 0x04F0 0x1 0x0 -#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x0244 0x04AC 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x0244 0x04AC 0x05EC 0x3 0x1 -#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x0244 0x04AC 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x0248 0x04B0 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x0248 0x04B0 0x0504 0x0 0x3 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x0248 0x04B0 0x04F0 0x1 0x1 -#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x0248 0x04B0 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x0248 0x04B0 0x0000 0x2 0x0 -#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x0248 0x04B0 0x05E8 0x3 0x1 -#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x0248 0x04B0 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x024C 0x04B4 0x050C 0x0 0x2 -#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x024C 0x04B4 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x024C 0x04B4 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x024C 0x04B4 0x04F8 0x1 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x024C 0x04B4 0x0000 0x3 0x0 -#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x024C 0x04B4 0x0000 0x5 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0250 0x04B8 0x0000 0x0 0x0 -#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x0250 0x04B8 0x050C 0x0 0x3 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x0250 0x04B8 0x04F8 0x1 0x1 -#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x0250 0x04B8 0x0000 0x1 0x0 -#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x0250 0x04B8 0x05F0 0x3 0x1 -#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x0250 0x04B8 0x0000 0x5 0x0 + +#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 +#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 +#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 +#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x030 0x298 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x030 0x298 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x030 0x298 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x034 0x29C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x034 0x29C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x034 0x29C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x034 0x29C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x038 0x2A0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x038 0x2A0 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x038 0x2A0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x038 0x2A0 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x03C 0x2A4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x03C 0x2A4 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x03C 0x2A4 0x4BC 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x03C 0x2A4 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x040 0x2A8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x040 0x2A8 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x040 0x2A8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x040 0x2A8 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x044 0x2AC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x044 0x2AC 0x4C0 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x044 0x2AC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x044 0x2AC 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x048 0x2B0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x048 0x2B0 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x048 0x2B0 0x000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x048 0x2B0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x048 0x2B0 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x04C 0x2B4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x04C 0x2B4 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x04C 0x2B4 0x000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x04C 0x2B4 0x000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x04C 0x2B4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x04C 0x2B4 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x050 0x2B8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x050 0x2B8 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x050 0x2B8 0x000 0x2 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x054 0x2BC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x054 0x2BC 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x054 0x2BC 0x000 0x4 0x0 +#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x054 0x2BC 0x4BC 0x5 0x1 +#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x054 0x2BC 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x058 0x2C0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x058 0x2C0 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x058 0x2C0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x058 0x2C0 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x05C 0x2C4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x05C 0x2C4 0x000 0x1 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x05C 0x2C4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x05C 0x2C4 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x060 0x2C8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x060 0x2C8 0x598 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x060 0x2C8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x060 0x2C8 0x000 0x6 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x064 0x2CC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x064 0x2CC 0x5B8 0x4 0x2 +#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x064 0x2CC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x064 0x2CC 0x000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x068 0x2D0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x068 0x2D0 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x068 0x2D0 0x540 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x068 0x2D0 0x000 0x4 0x0 +#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x068 0x2D0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x068 0x2D0 0x59C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x06C 0x2D4 0x4C0 0x0 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x06C 0x2D4 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x06C 0x2D4 0x53C 0x3 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x06C 0x2D4 0x5CC 0x4 0x1 +#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x06C 0x2D4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x06C 0x2D4 0x550 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x070 0x2D8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x070 0x2D8 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x070 0x2D8 0x538 0x3 0x1 +#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x070 0x2D8 0x568 0x4 0x1 +#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x070 0x2D8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x070 0x2D8 0x584 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x074 0x2DC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x074 0x2DC 0x5A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x074 0x2DC 0x5A4 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x074 0x2DC 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x074 0x2DC 0x540 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x074 0x2DC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x074 0x2DC 0x54C 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x078 0x2E0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x078 0x2E0 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x078 0x2E0 0x53C 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x078 0x2E0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x078 0x2E0 0x598 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x07C 0x2E4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x07C 0x2E4 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x07C 0x2E4 0x538 0x3 0x2 +#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x07C 0x2E4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x07C 0x2E4 0x5B8 0x6 0x3 +#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x080 0x2E8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x080 0x2E8 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x080 0x2E8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x080 0x2E8 0x5B4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x084 0x2EC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x084 0x2EC 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x084 0x2EC 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x084 0x2EC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x084 0x2EC 0x5B0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x088 0x2F0 0x574 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x088 0x2F0 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x088 0x2F0 0x540 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x088 0x2F0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x088 0x2F0 0x5E4 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x08C 0x2F4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x08C 0x2F4 0x5C8 0x1 0x0 +#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x08C 0x2F4 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x08C 0x2F4 0x53C 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x08C 0x2F4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x08C 0x2F4 0x5E0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090 0x2F8 0x57C 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x090 0x2F8 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x090 0x2F8 0x538 0x3 0x3 +#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x090 0x2F8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x090 0x2F8 0x558 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x094 0x2FC 0x554 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x094 0x2FC 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x094 0x2FC 0x534 0x3 0x1 +#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x094 0x2FC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x094 0x2FC 0x000 0x6 0x0 +#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x098 0x300 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x098 0x300 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x098 0x300 0x000 0x3 0x0 +#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x098 0x300 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x098 0x300 0x5A0 0x6 0x1 +#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x09C 0x304 0x000 0x0 0x0 +#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x09C 0x304 0x000 0x2 0x0 +#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x09C 0x304 0x5CC 0x3 0x5 +#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x09C 0x304 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x09C 0x304 0x5DC 0x6 0x1 +#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x0A0 0x308 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x0A0 0x308 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x0A0 0x308 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x0A0 0x308 0x4F4 0x4 0x4 +#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x0A0 0x308 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x0A4 0x30C 0x4C0 0x1 0x3 +#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x0A4 0x30C 0x4F4 0x4 0x5 +#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x0A4 0x30C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x0A8 0x310 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x0A8 0x310 0x4F0 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x0A8 0x310 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x0AC 0x314 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x0AC 0x314 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x0AC 0x314 0x4F0 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x0B0 0x318 0x57C 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x0B0 0x318 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x0B0 0x318 0x4FC 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x0B0 0x318 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0B4 0x31C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x0B4 0x31C 0x554 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x0B4 0x31C 0x4FC 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x0B4 0x31C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x0B4 0x31C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0B8 0x320 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x0B8 0x320 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x0B8 0x320 0x55C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x0B8 0x320 0x4F8 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x0B8 0x320 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0B8 0x320 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0BC 0x324 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x0BC 0x324 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x0BC 0x324 0x56C 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x0BC 0x324 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x0BC 0x324 0x4F8 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x0BC 0x324 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0C0 0x328 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x0C0 0x328 0x574 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x0C0 0x328 0x5D0 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x0C0 0x328 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x0C0 0x328 0x504 0x4 0x4 +#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x0C0 0x328 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0C4 0x32C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x0C4 0x32C 0x5C8 0x1 0x1 +#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x0C4 0x32C 0x560 0x3 0x1 +#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x0C4 0x32C 0x504 0x4 0x5 +#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x0C4 0x32C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x0C4 0x32C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x0C8 0x330 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x0C8 0x330 0x5A4 0x1 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0C8 0x330 0x5A4 0x1 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x0C8 0x330 0x588 0x3 0x1 +#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x0C8 0x330 0x500 0x4 0x2 +#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x0C8 0x330 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x0C8 0x330 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x0CC 0x334 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x0CC 0x334 0x5BC 0x3 0x1 +#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x0CC 0x334 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x0CC 0x334 0x500 0x4 0x3 +#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x0CC 0x334 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0D0 0x338 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0D0 0x338 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x0D0 0x338 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x0D4 0x33C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x0D4 0x33C 0x4E4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x0D4 0x33C 0x580 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x0D4 0x33C 0x50C 0x3 0x4 +#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x0D4 0x33C 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x0D4 0x33C 0x594 0x4 0x1 +#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x0D4 0x33C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x0D4 0x33C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0D8 0x340 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x0D8 0x340 0x4D0 0x1 0x1 +#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x0D8 0x340 0x590 0x2 0x1 +#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x0D8 0x340 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x0D8 0x340 0x50C 0x3 0x5 +#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x0D8 0x340 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x0D8 0x340 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x0D8 0x340 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0DC 0x344 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x0DC 0x344 0x4D4 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x0DC 0x344 0x58C 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x0DC 0x344 0x4FC 0x3 0x6 +#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x0DC 0x344 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x0DC 0x344 0x534 0x4 0x2 +#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x0DC 0x344 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x0DC 0x344 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0E0 0x348 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x0E0 0x348 0x4EC 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x0E0 0x348 0x5D4 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x0E0 0x348 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x0E0 0x348 0x4FC 0x3 0x7 +#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x0E0 0x348 0x538 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x0E0 0x348 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x0E0 0x348 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0E4 0x34C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x0E4 0x34C 0x4E8 0x1 0x1 +#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x0E4 0x34C 0x570 0x2 0x2 +#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x0E4 0x34C 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x0E4 0x34C 0x53C 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x0E4 0x34C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x0E4 0x34C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0E8 0x350 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x0E8 0x350 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x0E8 0x350 0x578 0x2 0x1 +#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x0E8 0x350 0x5CC 0x3 0x2 +#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x0E8 0x350 0x540 0x4 0x4 +#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x0E8 0x350 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x0E8 0x350 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x0EC 0x354 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x0EC 0x354 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x0EC 0x354 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x0F0 0x358 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x0F0 0x358 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x0F0 0x358 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x0F4 0x35C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x0F4 0x35C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x0F4 0x35C 0x534 0x3 0x3 +#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x0F4 0x35C 0x504 0x4 0x6 +#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x0F4 0x35C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x0F4 0x35C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x0F4 0x35C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x0F8 0x360 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x0F8 0x360 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x0F8 0x360 0x538 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x0F8 0x360 0x000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x0F8 0x360 0x504 0x4 0x7 +#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x0F8 0x360 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x0F8 0x360 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x0FC 0x364 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x0FC 0x364 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x0FC 0x364 0x59C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x0FC 0x364 0x534 0x3 0x4 +#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x0FC 0x364 0x5D4 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x0FC 0x364 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x0FC 0x364 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x100 0x368 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x100 0x368 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x100 0x368 0x550 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x100 0x368 0x538 0x3 0x6 +#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x100 0x368 0x58C 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x100 0x368 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x100 0x368 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x104 0x36C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x104 0x36C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x104 0x36C 0x584 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x104 0x36C 0x53C 0x3 0x5 +#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x104 0x36C 0x5BC 0x4 0x2 +#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x104 0x36C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x104 0x36C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x108 0x370 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x108 0x370 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x108 0x370 0x54C 0x2 0x0 +#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x108 0x370 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x108 0x370 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x10C 0x374 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x10C 0x374 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x10C 0x374 0x53C 0x3 0x6 +#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x10C 0x374 0x50C 0x4 0x6 +#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x10C 0x374 0x000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x10C 0x374 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x10C 0x374 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x110 0x378 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x110 0x378 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x110 0x378 0x540 0x3 0x5 +#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x110 0x378 0x000 0x4 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x110 0x378 0x50C 0x4 0x7 +#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x110 0x378 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x110 0x378 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x114 0x37C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x114 0x37C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x114 0x37C 0x598 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x114 0x37C 0x58C 0x4 0x3 +#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x114 0x37C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x114 0x37C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x118 0x380 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x118 0x380 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x118 0x380 0x5B8 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x118 0x380 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x118 0x380 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x11C 0x384 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x11C 0x384 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x11C 0x384 0x5B4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x11C 0x384 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x11C 0x384 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x120 0x388 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x120 0x388 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x120 0x388 0x5B0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x120 0x388 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x120 0x388 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x124 0x38C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x124 0x38C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x124 0x38C 0x5E4 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x124 0x38C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x124 0x38C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x12C 0x394 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x12C 0x394 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x12C 0x394 0x000 0x3 0x0 +#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x12C 0x394 0x588 0x4 0x2 +#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x12C 0x394 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x12C 0x394 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x130 0x398 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x130 0x398 0x000 0x1 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x130 0x398 0x558 0x2 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x130 0x398 0x538 0x3 0x7 +#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x130 0x398 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x134 0x39C 0x000 0x2 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x134 0x39C 0x540 0x3 0x6 +#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x134 0x39C 0x588 0x4 0x3 +#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x134 0x39C 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x138 0x3A0 0x5A0 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x138 0x3A0 0x5BC 0x4 0x3 +#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x138 0x3A0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x138 0x3A0 0x000 0x6 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x13C 0x3A4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x13C 0x3A4 0x5DC 0x2 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x13C 0x3A4 0x58C 0x4 0x4 +#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x13C 0x3A4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x13C 0x3A4 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x140 0x3A8 0x4E4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x140 0x3A8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x144 0x3AC 0x4D0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x144 0x3AC 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x144 0x3AC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x148 0x3B0 0x4D4 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x148 0x3B0 0x534 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x148 0x3B0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x14C 0x3B4 0x4D8 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x14C 0x3B4 0x4EC 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x14C 0x3B4 0x538 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x14C 0x3B4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x150 0x3B8 0x4DC 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x150 0x3B8 0x53C 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x154 0x3BC 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x154 0x3BC 0x540 0x4 0x0 +#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x154 0x3BC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x158 0x3C0 0x594 0x0 0x0 +#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x158 0x3C0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x1B0 0x418 0x000 0x2 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x1B0 0x418 0x5AC 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1B0 0x418 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x1B0 0x418 0x4F4 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x1B0 0x418 0x53C 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x1B4 0x41C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x1B4 0x41C 0x538 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x1B8 0x420 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x1B8 0x420 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x1B8 0x420 0x540 0x6 0x7 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x1BC 0x424 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 +#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x1BC 0x424 0x53C 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x1C0 0x428 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x1C0 0x428 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x1C0 0x428 0x538 0x6 0x9 +#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x1C4 0x42C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x1C4 0x42C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x1C4 0x42C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x1C4 0x42C 0x540 0x6 0x8 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x1C8 0x430 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x1C8 0x430 0x594 0x1 0x2 +#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1C8 0x430 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x1C8 0x430 0x5C0 0x6 0x1 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x1CC 0x434 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x1CC 0x434 0x5F0 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x1CC 0x434 0x4E4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x1CC 0x434 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x1CC 0x434 0x5CC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x1CC 0x434 0x534 0x6 0x5 +#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x5E8 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x1D0 0x438 0x5AC 0x3 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x1D0 0x438 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x1D4 0x43C 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x1D4 0x43C 0x538 0x6 0x10 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x5EC 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x1D8 0x440 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x1D8 0x440 0x540 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x1DC 0x444 0x000 0x3 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 +#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x1DC 0x444 0x53C 0x6 0x9 +#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x1E0 0x448 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x1E0 0x448 0x4E0 0x2 0x1 +#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x1E0 0x448 0x568 0x4 0x2 +#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1E0 0x448 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x1E0 0x448 0x000 0x6 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x1E4 0x44C 0x5C0 0x0 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x1E4 0x44C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x1E4 0x44C 0x594 0x2 0x3 +#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x1E4 0x44C 0x000 0x4 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1E4 0x44C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x1E4 0x44C 0x5CC 0x6 0x4 +#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x1E8 0x450 0x000 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x1E8 0x450 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1E8 0x450 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x1EC 0x454 0x5CC 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x1EC 0x454 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x1EC 0x454 0x000 0x5 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x1F0 0x458 0x568 0x0 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x1F0 0x458 0x000 0x1 0x0 +#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1F0 0x458 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x1F4 0x45C 0x5D8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1F4 0x45C 0x504 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x1F4 0x45C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x1F4 0x45C 0x55C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x1F4 0x45C 0x4DC 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x1F4 0x45C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x1F8 0x460 0x5A8 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1F8 0x460 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x1F8 0x460 0x504 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x1F8 0x460 0x56C 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x1F8 0x460 0x4D0 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x1F8 0x460 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1FC 0x464 0x5C4 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1FC 0x464 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x1FC 0x464 0x500 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x1FC 0x464 0x5D0 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x1FC 0x464 0x4D4 0x3 0x3 +#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x1FC 0x464 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x200 0x468 0x564 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x200 0x468 0x500 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x200 0x468 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x200 0x468 0x560 0x2 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x200 0x468 0x4D8 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x200 0x468 0x4EC 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x200 0x468 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x204 0x46C 0x580 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x204 0x46C 0x50C 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x204 0x46C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x204 0x46C 0x588 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x204 0x46C 0x000 0x3 0x0 +#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x204 0x46C 0x4E8 0x4 0x3 +#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x204 0x46C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x208 0x470 0x590 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x208 0x470 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x208 0x470 0x50C 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x208 0x470 0x5BC 0x2 0x4 +#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x208 0x470 0x4E0 0x3 0x2 +#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x208 0x470 0x000 0x4 0x0 +#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x208 0x470 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x20C 0x474 0x578 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x20C 0x474 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x20C 0x474 0x508 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x20C 0x474 0x5D4 0x2 0x3 +#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x20C 0x474 0x594 0x3 0x4 +#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x20C 0x474 0x000 0x5 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x210 0x478 0x570 0x0 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x210 0x478 0x508 0x1 0x1 +#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x210 0x478 0x000 0x1 0x0 +#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x210 0x478 0x58C 0x2 0x5 +#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x210 0x478 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x214 0x47C 0x55C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x214 0x47C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x214 0x47C 0x5D8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x214 0x47C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x218 0x480 0x56C 0x0 0x0 +#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x218 0x480 0x4C0 0x1 0x2 +#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x218 0x480 0x5A8 0x3 0x1 +#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x218 0x480 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x21C 0x484 0x5D0 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x21C 0x484 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x21C 0x484 0x598 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x21C 0x484 0x5C4 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x21C 0x484 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x220 0x488 0x560 0x0 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x220 0x488 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x220 0x488 0x5B8 0x2 0x1 +#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x220 0x488 0x564 0x3 0x1 +#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x220 0x488 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x224 0x48C 0x588 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x224 0x48C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x224 0x48C 0x000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x224 0x48C 0x580 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x224 0x48C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x228 0x490 0x5BC 0x0 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x228 0x490 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x228 0x490 0x000 0x2 0x0 +#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x228 0x490 0x590 0x3 0x2 +#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x228 0x490 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x22C 0x494 0x5D4 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x22C 0x494 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x22C 0x494 0x578 0x3 0x2 +#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x22C 0x494 0x000 0x5 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x230 0x498 0x58C 0x0 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x230 0x498 0x000 0x1 0x0 +#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x230 0x498 0x570 0x3 0x1 +#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x230 0x498 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x234 0x49C 0x4F4 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x234 0x49C 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x234 0x49C 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x234 0x49C 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x238 0x4A0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x238 0x4A0 0x4F4 0x0 0x1 +#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x238 0x4A0 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x238 0x4A0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x23C 0x4A4 0x4FC 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x23C 0x4A4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x23C 0x4A4 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x23C 0x4A4 0x000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x23C 0x4A4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x240 0x4A8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x240 0x4A8 0x4FC 0x0 0x1 +#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x240 0x4A8 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x240 0x4A8 0x000 0x3 0x0 +#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x240 0x4A8 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x244 0x4AC 0x504 0x0 0x2 +#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x244 0x4AC 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x244 0x4AC 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x244 0x4AC 0x4F0 0x1 0x0 +#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x244 0x4AC 0x000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x244 0x4AC 0x5EC 0x3 0x1 +#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x244 0x4AC 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x248 0x4B0 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x248 0x4B0 0x504 0x0 0x3 +#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x248 0x4B0 0x4F0 0x1 0x1 +#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x248 0x4B0 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x248 0x4B0 0x000 0x2 0x0 +#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x248 0x4B0 0x5E8 0x3 0x1 +#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x248 0x4B0 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x24C 0x4B4 0x50C 0x0 0x2 +#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x24C 0x4B4 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x24C 0x4B4 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x24C 0x4B4 0x4F8 0x1 0x0 +#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x24C 0x4B4 0x000 0x3 0x0 +#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x24C 0x4B4 0x000 0x5 0x0 +#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x250 0x4B8 0x000 0x0 0x0 +#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x250 0x4B8 0x50C 0x0 0x3 +#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x250 0x4B8 0x4F8 0x1 0x1 +#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x250 0x4B8 0x000 0x1 0x0 +#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x250 0x4B8 0x5F0 0x3 0x1 +#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x250 0x4B8 0x000 0x5 0x0 #endif /* __DTS_IMX8MN_PINFUNC_H */ diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index f5eff35986..ee17902304 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -7,11 +7,11 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8mn-pinfunc.h" / { - compatible = "fsl,imx8mn"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -43,6 +43,19 @@ #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -51,6 +64,11 @@ clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; + cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_1: cpu@1 { @@ -61,6 +79,9 @@ clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_2: cpu@2 { @@ -71,6 +92,9 @@ clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_3: cpu@3 { @@ -81,6 +105,9 @@ clocks = <&clk IMX8MN_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + cpu-idle-states = <&cpu_pd_wait>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -88,9 +115,33 @@ }; }; - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0xb00>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0x300>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x100>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; }; osc_32k: clock-osc-32k { @@ -135,17 +186,56 @@ clock-output-names = "clk_ext4"; }; + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tmu>; + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; clock-frequency = <8000000>; arm,no-tick-in-suspend; }; @@ -163,6 +253,149 @@ #size-cells = <1>; ranges; + spba: bus@30000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x100000>; + ranges; + + sai2: sai@30020000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30020000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI2_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI2_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@30030000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30030000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI3_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI3_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai5: sai@30050000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30050000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI5_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI5_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; + dma-names = "rx", "tx"; + fsl,shared-interrupt; + fsl,dataline = <0 0xf 0xf>; + status = "disabled"; + }; + + sai6: sai@30060000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x30060000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI6_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI6_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + micfil: audio-controller@30080000 { + compatible = "fsl,imx8mm-micfil"; + reg = <0x30080000 0x10000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_PDM_IPG>, + <&clk IMX8MN_CLK_PDM_ROOT>, + <&clk IMX8MN_AUDIO_PLL1_OUT>, + <&clk IMX8MN_AUDIO_PLL2_OUT>, + <&clk IMX8MN_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + + spdif1: spdif@30090000 { + compatible = "fsl,imx35-spdif"; + reg = <0x30090000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */ + <&clk IMX8MN_CLK_24M>, /* rxtx0 */ + <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8MN_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai7: sai@300b0000 { + compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; + reg = <0x300b0000 0x10000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SAI7_IPG>, + <&clk IMX8MN_CLK_DUMMY>, + <&clk IMX8MN_CLK_SAI7_ROOT>, + <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + easrc: easrc@300c0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x300c0000 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + }; + gpio1: gpio@30200000 { compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio"; reg = <0x30200000 0x10000>; @@ -173,6 +406,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 10 30>; }; gpio2: gpio@30210000 { @@ -185,6 +419,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 40 21>; }; gpio3: gpio@30220000 { @@ -197,6 +432,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 61 26>; }; gpio4: gpio@30230000 { @@ -209,6 +445,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 21 108 11>; }; gpio5: gpio@30240000 { @@ -221,6 +458,14 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 119 30>; + }; + + tmu: tmu@30260000 { + compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; }; wdog1: watchdog@30280000 { @@ -248,7 +493,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x302b0000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>, @@ -259,7 +504,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>, @@ -279,15 +524,21 @@ reg = <0x30340000 0x10000>; }; - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon"; + ocotp: efuse@30350000 { + compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>; + #address-cells = <1>; + #size-cells = <1>; + + cpu_speed_grade: speed-grade@10 { + reg = <0x10 4>; + }; }; anatop: anatop@30360000 { compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop", - "syscon", "simple-bus"; + "syscon"; reg = <0x30360000 0x10000>; }; @@ -301,6 +552,7 @@ offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; clock-names = "snvs-rtc"; }; @@ -308,6 +560,8 @@ compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_SNVS_ROOT>; + clock-names = "snvs-pwrkey"; linux,keycode = <KEY_POWER>; wakeup-source; status = "disabled"; @@ -322,10 +576,24 @@ <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>, + <&clk IMX8MN_CLK_A53_CORE>, + <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AUDIO_AHB>, + <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>, + <&clk IMX8MN_SYS_PLL3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_ARM_PLL_OUT>, + <&clk IMX8MN_SYS_PLL3_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, <0>, + <400000000>, + <400000000>, + <600000000>; }; src: reset-controller@30390000 { - compatible = "fsl,imx8mn-src", "syscon"; + compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; @@ -382,6 +650,14 @@ #pwm-cells = <2>; status = "disabled"; }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; }; aips3: bus@30800000 { @@ -467,6 +743,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_AHB>, + <&clk IMX8MN_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -519,16 +825,22 @@ status = "disabled"; }; + mu: mailbox@30aa0000 { + compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_MU_ROOT>; + #mbox-cells = <2>; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_DUMMY>, + clocks = <&clk IMX8MN_CLK_IPG_ROOT>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -539,7 +851,7 @@ compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_DUMMY>, + clocks = <&clk IMX8MN_CLK_IPG_ROOT>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; @@ -553,12 +865,10 @@ compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_DUMMY>, + clocks = <&clk IMX8MN_CLK_IPG_ROOT>, <&clk IMX8MN_CLK_NAND_USDHC_BUS>, <&clk IMX8MN_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -566,11 +876,11 @@ }; sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>, - <&clk IMX8MN_CLK_SDMA1_ROOT>; + <&clk IMX8MN_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; @@ -581,7 +891,8 @@ reg = <0x30be0000 0x10000>; interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_ENET1_ROOT>, <&clk IMX8MN_CLK_ENET1_ROOT>, <&clk IMX8MN_CLK_ENET_TIMER>, @@ -617,10 +928,8 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; status = "disabled"; @@ -631,28 +940,6 @@ #index-cells = <1>; reg = <0x32e40200 0x200>; }; - - usbotg2: usb@32e50000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; - reg = <0x32e50000 0x200>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; - clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, - <&clk IMX8MN_CLK_USB_CORE_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, - <&clk IMX8MN_SYS_PLL1_100M>; - fsl,usbphy = <&usbphynop2>; - fsl,usbmisc = <&usbmisc2 0>; - status = "disabled"; - }; - - usbmisc2: usbmisc@32e50200 { - compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; - #index-cells = <1>; - reg = <0x32e50200 0x200>; - }; - }; dma_apbh: dma-controller@33000000 { @@ -692,17 +979,25 @@ interrupt-controller; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; - }; - usbphynop1: usbphynop1 { - compatible = "usb-nop-xceiv"; - clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; - clock-names = "main_clk"; + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MN_CLK_DRAM_CORE>, + <&clk IMX8MN_DRAM_PLL>, + <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>; + }; + + ddr-pmu@3d800000 { + compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu"; + reg = <0x3d800000 0x400000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + }; }; - usbphynop2: usbphynop2 { + usbphynop1: usbphynop1 { compatible = "usb-nop-xceiv"; clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; |