diff options
| author | Tom Rini <trini@konsulko.com> | 2022-10-31 17:40:31 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-10-31 17:40:31 +0300 |
| commit | 6f38d91158e7e4199753b79e0a25c1a65175aba4 (patch) | |
| tree | 0ef14997a05c73d3d3a4640284d241d3e046ce4a /arch/arm | |
| parent | 218e2c45af83f2cb7b1374b9023b4ced6eb0bb77 (diff) | |
| parent | 21545a8cbf9ef3c47a1a8c347ad31e759b00b0c7 (diff) | |
| download | u-boot-6f38d91158e7e4199753b79e0a25c1a65175aba4.tar.xz | |
Merge branch '2022-10-31-broadcom-updates'
- Update / add a large number of Broadcom BCA SoCs.
Diffstat (limited to 'arch/arm')
72 files changed, 3068 insertions, 750 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6fb39e18d2..8bc9aaf010 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -678,31 +678,6 @@ config ARCH_BCM283X imply CMD_DM imply FAT_WRITE -config ARCH_BCM63158 - bool "Broadcom BCM63158 family" - select DM - select OF_CONTROL - imply CMD_DM - -config ARCH_BCM6753 - bool "Broadcom BCM6753 family" - select CPU_V7A - select DM - select OF_CONTROL - imply CMD_DM - -config ARCH_BCM68360 - bool "Broadcom BCM68360 family" - select DM - select OF_CONTROL - imply CMD_DM - -config ARCH_BCM6858 - bool "Broadcom BCM6858 family" - select DM - select OF_CONTROL - imply CMD_DM - config ARCH_BCMSTB bool "Broadcom BCM7XXX family" select CPU_V7A @@ -719,6 +694,7 @@ config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM select OF_CONTROL + imply CMD_DM config TARGET_VEXPRESS_CA9X4 bool "Support vexpress_ca9x4" @@ -2335,10 +2311,6 @@ source "board/Marvell/octeontx2/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" source "board/cortina/presidio-asic/Kconfig" -source "board/broadcom/bcm963158/Kconfig" -source "board/broadcom/bcm96753ref/Kconfig" -source "board/broadcom/bcm968360bg/Kconfig" -source "board/broadcom/bcm968580xref/Kconfig" source "board/broadcom/bcmns3/Kconfig" source "board/cavium/thunderx/Kconfig" source "board/eets/pdu001/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5c7cdc9847..791838733c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1164,24 +1164,43 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ bcm2837-rpi-cm3-io3.dtb \ bcm2711-rpi-4-b.dtb -dtb-$(CONFIG_ARCH_BCM63158) += \ - bcm963158.dtb - -dtb-$(CONFIG_ARCH_BCM68360) += \ - bcm968360bg.dtb - -dtb-$(CONFIG_ARCH_BCM6753) += \ - bcm96753ref.dtb - -dtb-$(CONFIG_ARCH_BCM6858) += \ - bcm968580xref.dtb - dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb dtb-$(CONFIG_BCM47622) += \ bcm947622.dtb +dtb-$(CONFIG_BCM4908) += \ + bcm94908.dtb +dtb-$(CONFIG_BCM4912) += \ + bcm94912.dtb +dtb-$(CONFIG_BCM63138) += \ + bcm963138.dtb +dtb-$(CONFIG_BCM63146) += \ + bcm963146.dtb +dtb-$(CONFIG_BCM63148) += \ + bcm963148.dtb +dtb-$(CONFIG_BCM63158) += \ + bcm963158.dtb +dtb-$(CONFIG_BCM63178) += \ + bcm963178.dtb +dtb-$(CONFIG_BCM6756) += \ + bcm96756.dtb +dtb-$(CONFIG_BCM6813) += \ + bcm96813.dtb +dtb-$(CONFIG_BCM6846) += \ + bcm96846.dtb +dtb-$(CONFIG_BCM6855) += \ + bcm96855.dtb \ + bcm96753ref.dtb +dtb-$(CONFIG_BCM6856) += \ + bcm96856.dtb \ + bcm968360bg.dtb +dtb-$(CONFIG_BCM6858) += \ + bcm96858.dtb \ + bcm968580xref.dtb +dtb-$(CONFIG_BCM6878) += \ + bcm96878.dtb dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi new file mode 100644 index 0000000000..0be5cfeeff --- /dev/null +++ b/arch/arm/dts/bcm4908.dtsi @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/dts-v1/; + +/ { + compatible = "brcm,bcm4908", "brcm,bcmbca"; + + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "brcm,brahma-b53"; + reg = <0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + clocks { + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0xff800000 0x3000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + }; +}; diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi new file mode 100644 index 0000000000..3d016c2ce6 --- /dev/null +++ b/arch/arm/dts/bcm4912.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm4912", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi new file mode 100644 index 0000000000..42b442aec9 --- /dev/null +++ b/arch/arm/dts/bcm63138.dtsi @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Broadcom BCM63138 DSL SoCs Device Tree + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63138", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + enable-method = "brcm,bcm63138"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <1>; + enable-method = "brcm,bcm63138"; + }; + }; + + clocks { + /* UBUS peripheral clock */ + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + + /* peripheral clock for system timer */ + axi_clk: axi_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* APB bus clock */ + apb_clk: apb_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&armpll>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x784000>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + cache-size = <524288>; + cache-sets = <1024>; + cache-line-size = <32>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + scu: scu@1e000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000 0x100>; + }; + + gic: interrupt-controller@1f000 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1f000 0x1000 + 0x1e100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer@1e200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1e200 0x20>; + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; + clocks = <&axi_clk>; + }; + + local_timer: local-timer@1e600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_EDGE_RISING)>; + clocks = <&axi_clk>; + }; + + twd_watchdog: watchdog@1e620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e620 0x20>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + + armpll: armpll@20000 { + #clock-cells = <0>; + compatible = "brcm,bcm63138-armpll"; + clocks = <&periph_clk>; + reg = <0x20000 0xf00>; + }; + }; + + /* Legacy UBUS base */ + bus@fffe8000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + timer0: timer@80 { + compatible = "brcm,bcmbca-periph-timer"; + reg = <0x80 0x28>; + clocks = <&periph_clk>; + }; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi new file mode 100644 index 0000000000..04de96bd0a --- /dev/null +++ b/arch/arm/dts/bcm63146.dtsi @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm63146", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi new file mode 100644 index 0000000000..df5307b6b3 --- /dev/null +++ b/arch/arm/dts/bcm63148.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63148", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + B15_0: cpu@0 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B15_1: cpu@1 { + device_type = "cpu"; + compatible = "brcm,brahma-b15"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B15_0>, <&B15_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@80030000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x80030000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8000>; + + uart0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x20>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi index 7dd2858438..8b179ba0fc 100644 --- a/arch/arm/dts/bcm63158.dtsi +++ b/arch/arm/dts/bcm63158.dtsi @@ -1,122 +1,167 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + * Copyright 2022 Broadcom Ltd. */ -#include "skeleton64.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { - compatible = "brcm,bcm63158"; + compatible = "brcm,bcm63158", "brcm,bcmbca"; #address-cells = <2>; #size-cells = <2>; - aliases { - spi0 = &hsspi; - }; + interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; - u-boot,dm-pre-reloc; - cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x0>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x1>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x2>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x3>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - l2: l2-cache0 { + L2_0: l2-cache0 { compatible = "cache"; - u-boot,dm-pre-reloc; }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; u-boot,dm-pre-reloc; - - periph_osc: periph-osc { + periph_clk: periph-clk { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <0xbebc200>; - u-boot,dm-pre-reloc; + clock-frequency = <200000000>; }; hsspi_pll: hsspi-pll { compatible = "fixed-factor-clock"; #clock-cells = <0>; - clocks = <&periph_osc>; + clocks = <&periph_clk>; clock-mult = <2>; clock-div = <1>; }; - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; #clock-cells = <0>; - clock-frequency = <50000000>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; }; }; - ubus { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; u-boot,dm-pre-reloc; - uart0: serial@ff812000 { + uart0: serial@12000 { compatible = "arm,pl011", "arm,primecell"; - reg = <0x0 0xff812000 0x0 0x1000>; - clock = <50000000>; - + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; status = "disabled"; }; - leds: led-controller@ff800800 { + leds: led-controller@800 { compatible = "brcm,bcm6858-leds"; - reg = <0x0 0xff800800 0x0 0xe4>; + reg = <0x800 0xe4>; status = "disabled"; }; - wdt1: watchdog@ff800480 { + wdt1: watchdog@480 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff800480 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x480 0x14>; + clocks = <&wdt_clk>; }; - wdt2: watchdog@ff8004c0 { + wdt2: watchdog@4c0 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff8004c0 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x4c0 0x14>; + clocks = <&wdt_clk>; }; wdt-reboot { @@ -124,91 +169,91 @@ wdt = <&wdt1>; }; - gpio0: gpio-controller@0xff800500 { + gpio0: gpio-controller@500 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800500 0x0 0x4>, - <0x0 0xff800520 0x0 0x4>; + reg = <0x500 0x4>, + <0x520 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio1: gpio-controller@0xff800504 { + gpio1: gpio-controller@504 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800504 0x0 0x4>, - <0x0 0xff800524 0x0 0x4>; + reg = <0x504 0x4>, + <0x524 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio2: gpio-controller@0xff800508 { + gpio2: gpio-controller@508 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800508 0x0 0x4>, - <0x0 0xff800528 0x0 0x4>; + reg = <0x508 0x4>, + <0x528 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio3: gpio-controller@0xff80050c { + gpio3: gpio-controller@50c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80050c 0x0 0x4>, - <0x0 0xff80052c 0x0 0x4>; + reg = <0x50c 0x4>, + <0x52c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio4: gpio-controller@0xff800510 { + gpio4: gpio-controller@510 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800510 0x0 0x4>, - <0x0 0xff800530 0x0 0x4>; + reg = <0x510 0x4>, + <0x530 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio5: gpio-controller@0xff800514 { + gpio5: gpio-controller@514 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800514 0x0 0x4>, - <0x0 0xff800534 0x0 0x4>; + reg = <0x514 0x4>, + <0x534 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio6: gpio-controller@0xff800518 { + gpio6: gpio-controller@518 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800518 0x0 0x4>, - <0x0 0xff800538 0x0 0x4>; + reg = <0x518 0x4>, + <0x538 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio7: gpio-controller@0xff80051c { + gpio7: gpio-controller@51c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80051c 0x0 0x4>, - <0x0 0xff80053c 0x0 0x4>; + reg = <0x51c 0x4>, + <0x53c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - hsspi: spi-controller@ff801000 { + hsspi: spi-controller@1000 { compatible = "brcm,bcm6328-hsspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0xff801000 0x0 0x600>; + reg = <0x1000 0x600>; clocks = <&hsspi_pll>, <&hsspi_pll>; clock-names = "hsspi", "pll"; spi-max-frequency = <100000000>; @@ -217,14 +262,14 @@ status = "disabled"; }; - nand: nand-controller@ff801800 { + nand: nand-controller@1800 { compatible = "brcm,nand-bcm63158", "brcm,brcmnand-v5.0", "brcm,brcmnand"; reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x0 0xff801800 0x0 0x180>, - <0x0 0xff802000 0x0 0x10>, - <0x0 0xff801c00 0x0 0x200>; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; parameter-page-big-endian = <0>; status = "disabled"; diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi new file mode 100644 index 0000000000..cbd094dde6 --- /dev/null +++ b/arch/arm/dts/bcm63178.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm63178", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm6753.dtsi b/arch/arm/dts/bcm6753.dtsi deleted file mode 100644 index e88ab095c2..0000000000 --- a/arch/arm/dts/bcm6753.dtsi +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com> - */ - -#include "skeleton.dtsi" - -/ { - compatible = "brcm,bcm6753"; - #address-cells = <1>; - #size-cells = <1>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - u-boot,dm-pre-reloc; - - cpu0: cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x1>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0x2>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; - }; - - l2: l2-cache0 { - compatible = "cache"; - u-boot,dm-pre-reloc; - }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - u-boot,dm-pre-reloc; - - periph_osc: periph-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - u-boot,dm-pre-reloc; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_osc>; - clock-mult = <2>; - clock-div = <1>; - }; - - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - }; - - ubus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - u-boot,dm-pre-reloc; - - uart0: serial@ff812000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0xff812000 0x1000>; - clock = <50000000>; - - status = "disabled"; - }; - - wdt1: watchdog@ff800480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0xff800480 0x14>; - clocks = <&refclk50mhz>; - }; - - wdt2: watchdog@ff8004c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0xff8004c0 0x14>; - clocks = <&refclk50mhz>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - gpio0: gpio-controller@0xff800500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800500 0x4>, - <0xff800520 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@0xff800504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800504 0x4>, - <0xff800524 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@0xff800508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800508 0x4>, - <0xff800528 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@0xff80050c { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff80050c 0x4>, - <0xff80052c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@0xff800510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800510 0x4>, - <0xff800530 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@0xff800514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800514 0x4>, - <0xff800534 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@0xff800518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff800518 0x4>, - <0xff800538 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@0xff80051c { - compatible = "brcm,bcm6345-gpio"; - reg = <0xff80051c 0x4>, - <0xff80053c 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - nand: nand-controller@ff801800 { - compatible = "brcm,nand-bcm6753", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0xff801800 0x180>, - <0xff802000 0x10>, - <0xff801c00 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - - leds: led-controller@ff803000 { - compatible = "brcm,bcm6753-leds"; - reg = <0xff803000 0x3480>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6756.dtsi b/arch/arm/dts/bcm6756.dtsi new file mode 100644 index 0000000000..ce1b59faf8 --- /dev/null +++ b/arch/arm/dts/bcm6756.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6756", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>, <&CA7_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm6813.dtsi b/arch/arm/dts/bcm6813.dtsi new file mode 100644 index 0000000000..c3e6197be8 --- /dev/null +++ b/arch/arm/dts/bcm6813.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6813", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x3>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm68360.dtsi b/arch/arm/dts/bcm68360.dtsi deleted file mode 100644 index 7bbe207794..0000000000 --- a/arch/arm/dts/bcm68360.dtsi +++ /dev/null @@ -1,217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> - */ - -#include "skeleton64.dtsi" - -/ { - compatible = "brcm,bcm68360"; - #address-cells = <2>; - #size-cells = <2>; - - aliases { - spi0 = &hsspi; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - u-boot,dm-pre-reloc; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; - device_type = "cpu"; - reg = <0x0 0x0>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; - device_type = "cpu"; - reg = <0x0 0x1>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; - }; - - l2: l2-cache0 { - compatible = "cache"; - u-boot,dm-pre-reloc; - }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - u-boot,dm-pre-reloc; - - periph_osc: periph-osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - u-boot,dm-pre-reloc; - }; - - hsspi_pll: hsspi-pll { - compatible = "fixed-factor-clock"; - #clock-cells = <0>; - clocks = <&periph_osc>; - clock-mult = <2>; - clock-div = <1>; - }; - - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - }; - - ubus { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - u-boot,dm-pre-reloc; - - wdt1: watchdog@ff800480 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff800480 0x0 0x14>; - clocks = <&refclk50mhz>; - }; - - wdt2: watchdog@ff8004c0 { - compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff8004c0 0x0 0x14>; - clocks = <&refclk50mhz>; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdt1>; - }; - - uart0: serial@ff800640 { - compatible = "brcm,bcm6345-uart"; - reg = <0x0 0xff800640 0x0 0x18>; - clocks = <&periph_osc>; - - status = "disabled"; - }; - - leds: led-controller@ff800800 { - compatible = "brcm,bcm6858-leds"; - reg = <0x0 0xff800800 0x0 0xe4>; - - status = "disabled"; - }; - - gpio0: gpio-controller@0xff800500 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800500 0x0 0x4>, - <0x0 0xff800520 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio1: gpio-controller@0xff800504 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800504 0x0 0x4>, - <0x0 0xff800524 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio2: gpio-controller@0xff800508 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800508 0x0 0x4>, - <0x0 0xff800528 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio3: gpio-controller@0xff80050c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80050c 0x0 0x4>, - <0x0 0xff80052c 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio4: gpio-controller@0xff800510 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800510 0x0 0x4>, - <0x0 0xff800530 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio5: gpio-controller@0xff800514 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800514 0x0 0x4>, - <0x0 0xff800534 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio6: gpio-controller@0xff800518 { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800518 0x0 0x4>, - <0x0 0xff800538 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - gpio7: gpio-controller@0xff80051c { - compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80051c 0x0 0x4>, - <0x0 0xff80053c 0x0 0x4>; - gpio-controller; - #gpio-cells = <2>; - - status = "disabled"; - }; - - hsspi: spi-controller@ff801000 { - compatible = "brcm,bcm6328-hsspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0xff801000 0x0 0x600>; - clocks = <&hsspi_pll>, <&hsspi_pll>; - clock-names = "hsspi", "pll"; - spi-max-frequency = <100000000>; - num-cs = <8>; - - status = "disabled"; - }; - - nand: nand-controller@ff801800 { - compatible = "brcm,nand-bcm68360", - "brcm,brcmnand-v5.0", - "brcm,brcmnand"; - reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x0 0xff801800 0x0 0x180>, - <0x0 0xff802000 0x0 0x10>, - <0x0 0xff801c00 0x0 0x200>; - parameter-page-big-endian = <0>; - - status = "disabled"; - }; - }; -}; diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi new file mode 100644 index 0000000000..8aa47a2583 --- /dev/null +++ b/arch/arm/dts/bcm6846.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6846", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x1b>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi new file mode 100644 index 0000000000..05e0a4e0da --- /dev/null +++ b/arch/arm/dts/bcm6855.dtsi @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com> + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6855", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>; + }; + + clocks: clocks { + u-boot,dm-pre-reloc; + + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-mult = <2>; + clock-div = <1>; + }; + + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + u-boot,dm-pre-reloc; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + wdt1: watchdog@480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x480 0x14>; + clocks = <&wdt_clk>; + }; + + wdt2: watchdog@4c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x4c0 0x14>; + clocks = <&wdt_clk>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x4>, + <0x520 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x4>, + <0x524 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x4>, + <0x528 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x4>, + <0x52c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x4>, + <0x530 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x4>, + <0x534 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x4>, + <0x538 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x4>, + <0x53c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + nand: nand-controller@1800 { + compatible = "brcm,nand-bcm6753", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; + + leds: led-controller@3000 { + compatible = "brcm,bcm6753-leds"; + reg = <0x3000 0x3480>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi new file mode 100644 index 0000000000..99185ab0bc --- /dev/null +++ b/arch/arm/dts/bcm6856.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com> + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "brcm,bcm6856", "brcm,bcmbca"; + #address-cells = <2>; + #size-cells = <2>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; + device_type = "cpu"; + reg = <0x0 0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>; + }; + + clocks: clocks { + u-boot,dm-pre-reloc; + + periph_clk:periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + hsspi_pll: hsspi-pll { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-mult = <2>; + clock-div = <1>; + }; + + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; + u-boot,dm-pre-reloc; + + uart0: serial@640 { + compatible = "brcm,bcm6345-uart"; + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; + status = "disabled"; + }; + + wdt1: watchdog@480 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x480 0x14>; + clocks = <&wdt_clk>; + }; + + wdt2: watchdog@4c0 { + compatible = "brcm,bcm6345-wdt"; + reg = <0x4c0 0x14>; + clocks = <&wdt_clk>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt1>; + }; + + leds: led-controller@800 { + compatible = "brcm,bcm6858-leds"; + reg = <0x800 0xe4>; + + status = "disabled"; + }; + + gpio0: gpio-controller@500 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x500 0x4>, + <0x520 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio1: gpio-controller@504 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x504 0x4>, + <0x524 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio2: gpio-controller@508 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x508 0x4>, + <0x528 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio3: gpio-controller@50c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x50c 0x4>, + <0x52c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio4: gpio-controller@510 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x510 0x4>, + <0x530 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio5: gpio-controller@514 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x514 0x4>, + <0x534 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio6: gpio-controller@518 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x518 0x4>, + <0x538 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + gpio7: gpio-controller@51c { + compatible = "brcm,bcm6345-gpio"; + reg = <0x51c 0x4>, + <0x53c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + hsspi: spi-controller@1000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1000 0x600>; + clocks = <&hsspi_pll>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + spi-max-frequency = <100000000>; + num-cs = <8>; + + status = "disabled"; + }; + + nand: nand-controller@1800 { + compatible = "brcm,nand-bcm68360", + "brcm,brcmnand-v5.0", + "brcm,brcmnand"; + reg-names = "nand", "nand-int-base", "nand-cache"; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; + parameter-page-big-endian = <0>; + + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi index 0222562171..19c4dd6fa7 100644 --- a/arch/arm/dts/bcm6858.dtsi +++ b/arch/arm/dts/bcm6858.dtsi @@ -1,122 +1,161 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com> + * Copyright 2022 Broadcom Ltd. */ -#include "skeleton64.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { - compatible = "brcm,bcm6858"; + compatible = "brcm,bcm6858", "brcm,bcmbca"; #address-cells = <2>; #size-cells = <2>; - aliases { - spi0 = &hsspi; - }; + interrupt-parent = <&gic>; cpus { #address-cells = <2>; #size-cells = <0>; - u-boot,dm-pre-reloc; - cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_0: cpu@0 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x0>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_1: cpu@1 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x1>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_2: cpu@2 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x2>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + B53_3: cpu@3 { + compatible = "brcm,brahma-b53"; device_type = "cpu"; reg = <0x0 0x3>; - next-level-cache = <&l2>; - u-boot,dm-pre-reloc; + next-level-cache = <&L2_0>; + enable-method = "psci"; }; - l2: l2-cache0 { + L2_0: l2-cache0 { compatible = "cache"; - u-boot,dm-pre-reloc; }; }; + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&B53_0>, <&B53_1>, + <&B53_2>, <&B53_3>; + }; + clocks { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; u-boot,dm-pre-reloc; - periph_osc: periph-osc { + periph_clk: periph_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <200000000>; - u-boot,dm-pre-reloc; }; hsspi_pll: hsspi-pll { compatible = "fixed-factor-clock"; #clock-cells = <0>; - clocks = <&periph_osc>; + clocks = <&periph_clk>; clock-mult = <2>; clock-div = <1>; }; - refclk50mhz: refclk50mhz { - compatible = "fixed-clock"; + wdt_clk: wdt-clk { + compatible = "fixed-factor-clock"; #clock-cells = <0>; - clock-frequency = <50000000>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; }; }; - ubus { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, /* GICD */ + <0x2000 0x2000>, /* GICC */ + <0x4000 0x2000>, /* GICH */ + <0x6000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff800000 0x800000>; u-boot,dm-pre-reloc; - uart0: serial@ff800640 { + uart0: serial@640 { compatible = "brcm,bcm6345-uart"; - reg = <0x0 0xff800640 0x0 0x18>; - clocks = <&periph_osc>; - + reg = <0x640 0x18>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + clock-names = "refclk"; status = "disabled"; }; - leds: led-controller@ff800800 { + leds: led-controller@800 { compatible = "brcm,bcm6858-leds"; - reg = <0x0 0xff800800 0x0 0xe4>; + reg = <0x800 0xe4>; status = "disabled"; }; - wdt1: watchdog@ff802780 { + wdt1: watchdog@2780 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff802780 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x2780 0x14>; + clocks = <&wdt_clk>; }; - wdt2: watchdog@ff8027c0 { + wdt2: watchdog@27c0 { compatible = "brcm,bcm6345-wdt"; - reg = <0x0 0xff8027c0 0x0 0x14>; - clocks = <&refclk50mhz>; + reg = <0x27c0 0x14>; + clocks = <&wdt_clk>; }; wdt-reboot { @@ -124,91 +163,91 @@ wdt = <&wdt1>; }; - gpio0: gpio-controller@0xff800500 { + gpio0: gpio-controller@500 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800500 0x0 0x4>, - <0x0 0xff800520 0x0 0x4>; + reg = <0x500 0x4>, + <0x520 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio1: gpio-controller@0xff800504 { + gpio1: gpio-controller@504 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800504 0x0 0x4>, - <0x0 0xff800524 0x0 0x4>; + reg = <0x504 0x4>, + <0x524 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio2: gpio-controller@0xff800508 { + gpio2: gpio-controller@508 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800508 0x0 0x4>, - <0x0 0xff800528 0x0 0x4>; + reg = <0x508 0x4>, + <0x528 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio3: gpio-controller@0xff80050c { + gpio3: gpio-controller@50c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80050c 0x0 0x4>, - <0x0 0xff80052c 0x0 0x4>; + reg = <0x50c 0x4>, + <0x52c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio4: gpio-controller@0xff800510 { + gpio4: gpio-controller@510 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800510 0x0 0x4>, - <0x0 0xff800530 0x0 0x4>; + reg = <0x510 0x4>, + <0x530 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio5: gpio-controller@0xff800514 { + gpio5: gpio-controller@514 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800514 0x0 0x4>, - <0x0 0xff800534 0x0 0x4>; + reg = <0x514 0x4>, + <0x534 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio6: gpio-controller@0xff800518 { + gpio6: gpio-controller@518 { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff800518 0x0 0x4>, - <0x0 0xff800538 0x0 0x4>; + reg = <0x518 0x4>, + <0x538 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio7: gpio-controller@0xff80051c { + gpio7: gpio-controller@51c { compatible = "brcm,bcm6345-gpio"; - reg = <0x0 0xff80051c 0x0 0x4>, - <0x0 0xff80053c 0x0 0x4>; + reg = <0x51c 0x4>, + <0x53c 0x4>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - hsspi: spi-controller@ff801000 { + hsspi: spi-controller@1000 { compatible = "brcm,bcm6328-hsspi"; #address-cells = <1>; #size-cells = <0>; - reg = <0x0 0xff801000 0x0 0x600>; + reg = <0x1000 0x600>; clocks = <&hsspi_pll>, <&hsspi_pll>; clock-names = "hsspi", "pll"; spi-max-frequency = <100000000>; @@ -217,14 +256,14 @@ status = "disabled"; }; - nand: nand-controller@ff801800 { + nand: nand-controller@1800 { compatible = "brcm,nand-bcm6858", "brcm,brcmnand-v5.0", "brcm,brcmnand"; reg-names = "nand", "nand-int-base", "nand-cache"; - reg = <0x0 0xff801800 0x0 0x180>, - <0x0 0xff802000 0x0 0x10>, - <0x0 0xff801c00 0x0 0x200>; + reg = <0x1800 0x180>, + <0x2000 0x10>, + <0x1c00 0x200>; parameter-page-big-endian = <0>; status = "disabled"; diff --git a/arch/arm/dts/bcm6878.dtsi b/arch/arm/dts/bcm6878.dtsi new file mode 100644 index 0000000000..1e8b5fa96c --- /dev/null +++ b/arch/arm/dts/bcm6878.dtsi @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "brcm,bcm6878", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CA7_0>, <&CA7_1>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x8000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>, + <0x4000 0x2000>, + <0x6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/bcm94908.dts b/arch/arm/dts/bcm94908.dts new file mode 100644 index 0000000000..fcbd3c430a --- /dev/null +++ b/arch/arm/dts/bcm94908.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4908.dtsi" + +/ { + model = "Broadcom BCM94908 Reference Board"; + compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts new file mode 100644 index 0000000000..a3623e6f69 --- /dev/null +++ b/arch/arm/dts/bcm94912.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm4912.dtsi" + +/ { + model = "Broadcom BCM94912 Reference Board"; + compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963138.dts b/arch/arm/dts/bcm963138.dts new file mode 100644 index 0000000000..6158a87335 --- /dev/null +++ b/arch/arm/dts/bcm963138.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + model = "Broadcom BCM963138 Reference Board"; + compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts new file mode 100644 index 0000000000..e39f1e6d47 --- /dev/null +++ b/arch/arm/dts/bcm963146.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63146.dtsi" + +/ { + model = "Broadcom BCM963146 Reference Board"; + compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963148.dts b/arch/arm/dts/bcm963148.dts new file mode 100644 index 0000000000..98f6a6d09f --- /dev/null +++ b/arch/arm/dts/bcm963148.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63148.dtsi" + +/ { + model = "Broadcom BCM963148 Reference Board"; + compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts index c2bdd33274..eba07e0b1c 100644 --- a/arch/arm/dts/bcm963158.dts +++ b/arch/arm/dts/bcm963158.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com> + * Copyright 2022 Broadcom Ltd. */ /dts-v1/; @@ -8,8 +8,8 @@ #include "bcm63158.dtsi" / { - model = "Broadcom bcm963158"; - compatible = "broadcom,bcm963158", "brcm,bcm63158"; + model = "Broadcom BCM963158 Reference Board"; + compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca"; aliases { serial0 = &uart0; @@ -19,121 +19,12 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x0 0x40000000>; + reg = <0x0 0x0 0x0 0x08000000>; }; }; &uart0 { - u-boot,dm-pre-reloc; status = "okay"; }; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&gpio3 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&gpio6 { - status = "okay"; -}; - -&gpio7 { - status = "okay"; -}; - -&nand { - status = "okay"; - write-protect = <0>; - #address-cells = <1>; - #size-cells = <0>; - - nandcs@0 { - compatible = "brcm,nandcs"; - reg = <0>; - nand-ecc-strength = <4>; - nand-ecc-step-size = <512>; - brcm,nand-oob-sector-size = <16>; - }; -}; - -&leds { - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - brcm,serial-led-en-pol; - brcm,serial-led-data-ppol; - - led@16 { - reg = <16>; - label = "red:dsl2"; - }; - - led@17 { - reg = <17>; - label = "green:dsl1"; - }; - - led@18 { - reg = <18>; - label = "green:fxs2"; - }; - - led@19 { - reg = <19>; - label = "green:fxs1"; - }; - - led@26 { - reg = <26>; - label = "green:wan1_act"; - }; - - led@27 { - reg = <27>; - label = "green:wps"; - }; - - led@28 { - reg = <28>; - active-low; - label = "green:aggregate_act"; - }; - - led@29 { - reg = <29>; - label = "green:aggregate_link"; - }; -}; - -&hsspi { - status = "okay"; - - flash: mt25@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - spi-max-frequency = <25000000>; - }; -}; diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts new file mode 100644 index 0000000000..fa096e9cde --- /dev/null +++ b/arch/arm/dts/bcm963178.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63178.dtsi" + +/ { + model = "Broadcom BCM963178 Reference Board"; + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96753ref.dts b/arch/arm/dts/bcm96753ref.dts index ca15ca5f10..f74137f18f 100644 --- a/arch/arm/dts/bcm96753ref.dts +++ b/arch/arm/dts/bcm96753ref.dts @@ -5,13 +5,13 @@ /dts-v1/; -#include "bcm6753.dtsi" +#include "bcm6855.dtsi" #include <dt-bindings/gpio/gpio.h> / { - model = "Broadcom bcm6753ref"; - compatible = "broadcom,bcm6753ref", "brcm,bcm6753"; + model = "Broadcom BCM96753REF Reference Board"; + compatible = "brcm,bcm96753ref", "brcm,bcm6855", "brcm,bcmbca"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts new file mode 100644 index 0000000000..9a4a87ba9c --- /dev/null +++ b/arch/arm/dts/bcm96756.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6756.dtsi" + +/ { + model = "Broadcom BCM96756 Reference Board"; + compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96813.dts b/arch/arm/dts/bcm96813.dts new file mode 100644 index 0000000000..af17091ae7 --- /dev/null +++ b/arch/arm/dts/bcm96813.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6813.dtsi" + +/ { + model = "Broadcom BCM96813 Reference Board"; + compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm968360bg.dts b/arch/arm/dts/bcm968360bg.dts index c060294cc9..6f1090aa8e 100644 --- a/arch/arm/dts/bcm968360bg.dts +++ b/arch/arm/dts/bcm968360bg.dts @@ -5,11 +5,11 @@ /dts-v1/; -#include "bcm68360.dtsi" +#include "bcm6856.dtsi" / { - model = "Broadcom bcm68360bg"; - compatible = "broadcom,bcm68360bg", "brcm,bcm68360"; + model = "Broadcom BCM968360BG Reference Board"; + compatible = "brcm,bcm968360bg", "brcm,bcm6856", "brcm,bcmbca"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts new file mode 100644 index 0000000000..c70ebccabc --- /dev/null +++ b/arch/arm/dts/bcm96846.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6846.dtsi" + +/ { + model = "Broadcom BCM96846 Reference Board"; + compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts new file mode 100644 index 0000000000..e4e740c73e --- /dev/null +++ b/arch/arm/dts/bcm96855.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6855.dtsi" + +/ { + model = "Broadcom BCM96855 Reference Board"; + compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts new file mode 100644 index 0000000000..032aeb75c9 --- /dev/null +++ b/arch/arm/dts/bcm96856.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6856.dtsi" + +/ { + model = "Broadcom BCM96856 Reference Board"; + compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts new file mode 100644 index 0000000000..0cbf582f5d --- /dev/null +++ b/arch/arm/dts/bcm96858.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6858.dtsi" + +/ { + model = "Broadcom BCM96858 Reference Board"; + compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts index a034e38318..6d787bd011 100644 --- a/arch/arm/dts/bcm968580xref.dts +++ b/arch/arm/dts/bcm968580xref.dts @@ -8,8 +8,8 @@ #include "bcm6858.dtsi" / { - model = "Broadcom bcm68580xref"; - compatible = "broadcom,bcm68580xref", "brcm,bcm6858"; + model = "Broadcom BCM968580xref Reference Board"; + compatible = "brcm,bcm968580xref", "brcm,bcm6858", "brcm,bcmbca"; aliases { serial0 = &uart0; diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts new file mode 100644 index 0000000000..8fbc175cb4 --- /dev/null +++ b/arch/arm/dts/bcm96878.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm6878.dtsi" + +/ { + model = "Broadcom BCM96878 Reference Board"; + compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 2d49380f87..62b371612b 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -12,6 +12,128 @@ config BCM47622 select DM_SERIAL select PL01X_SERIAL -endif +config BCM4908 + bool "Support for Broadcom 4908 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select BCM6345_SERIAL + +config BCM4912 + bool "Support for Broadcom 4912 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select PL01X_SERIAL + +config BCM63138 + bool "Support for Broadcom 63138 Family" + select TIMER + select ARM_GLOBAL_TIMER + select CPU_V7A + select DM_SERIAL + select BCM6345_SERIAL + +config BCM63146 + bool "Support for Broadcom 63146 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select PL01X_SERIAL + +config BCM63148 + bool "Support for Broadcom 63148 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select BCM6345_SERIAL + +config BCM63158 + bool "Support for Broadcom 63158 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select PL01X_SERIAL + +config BCM63178 + bool "Support for Broadcom 63178 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL + +config BCM6756 + bool "Support for Broadcom 6756 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL + +config BCM6813 + bool "Support for Broadcom 6813 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select PL01X_SERIAL + +config BCM6846 + bool "Support for Broadcom 6846 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select BCM6345_SERIAL + +config BCM6855 + bool "Support for Broadcom 6855 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL + help + Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway + SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. + +config BCM6856 + bool "Support for Broadcom 6856 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select BCM6345_SERIAL + help + Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway + SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. + +config BCM6858 + bool "Support for Broadcom 6858 Family" + select ARM64 + select SYS_ARCH_TIMER + select DM_SERIAL + select BCM6345_SERIAL + help + Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway + SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. + +config BCM6878 + bool "Support for Broadcom 6878 Family" + select SYS_ARCH_TIMER + select CPU_V7A + select DM_SERIAL + select PL01X_SERIAL source "arch/arm/mach-bcmbca/bcm47622/Kconfig" +source "arch/arm/mach-bcmbca/bcm4908/Kconfig" +source "arch/arm/mach-bcmbca/bcm4912/Kconfig" +source "arch/arm/mach-bcmbca/bcm63138/Kconfig" +source "arch/arm/mach-bcmbca/bcm63146/Kconfig" +source "arch/arm/mach-bcmbca/bcm63148/Kconfig" +source "arch/arm/mach-bcmbca/bcm63158/Kconfig" +source "arch/arm/mach-bcmbca/bcm63178/Kconfig" +source "arch/arm/mach-bcmbca/bcm6756/Kconfig" +source "arch/arm/mach-bcmbca/bcm6813/Kconfig" +source "arch/arm/mach-bcmbca/bcm6846/Kconfig" +source "arch/arm/mach-bcmbca/bcm6855/Kconfig" +source "arch/arm/mach-bcmbca/bcm6856/Kconfig" +source "arch/arm/mach-bcmbca/bcm6858/Kconfig" +source "arch/arm/mach-bcmbca/bcm6878/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile index 072d4ea7b5..7de9450e19 100644 --- a/arch/arm/mach-bcmbca/Makefile +++ b/arch/arm/mach-bcmbca/Makefile @@ -4,3 +4,17 @@ # obj-$(CONFIG_BCM47622) += bcm47622/ +obj-$(CONFIG_BCM4908) += bcm4908/ +obj-$(CONFIG_BCM4912) += bcm4912/ +obj-$(CONFIG_BCM63138) += bcm63138/ +obj-$(CONFIG_BCM63146) += bcm63146/ +obj-$(CONFIG_BCM63148) += bcm63148/ +obj-$(CONFIG_BCM63158) += bcm63158/ +obj-$(CONFIG_BCM63178) += bcm63178/ +obj-$(CONFIG_BCM6756) += bcm6756/ +obj-$(CONFIG_BCM6813) += bcm6813/ +obj-$(CONFIG_BCM6846) += bcm6846/ +obj-$(CONFIG_BCM6855) += bcm6855/ +obj-$(CONFIG_BCM6856) += bcm6856/ +obj-$(CONFIG_BCM6858) += bcm6858/ +obj-$(CONFIG_BCM6878) += bcm6878/ diff --git a/arch/arm/mach-bcmbca/bcm4908/Kconfig b/arch/arm/mach-bcmbca/bcm4908/Kconfig new file mode 100644 index 0000000000..564bc8d2d6 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4908/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM4908 + +config TARGET_BCM94908 + bool "Broadcom 4908 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm4908" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm4908/Makefile b/arch/arm/mach-bcmbca/bcm4908/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4908/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c new file mode 100644 index 0000000000..5ab04083cc --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm94908_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm94908_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig new file mode 100644 index 0000000000..b8c14d1dc1 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM4912 + +config TARGET_BCM94912 + bool "Broadcom 4912 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm4912" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm4912/Makefile b/arch/arm/mach-bcmbca/bcm4912/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c new file mode 100644 index 0000000000..52a53a2c76 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm94912_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm94912_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm63138/Kconfig b/arch/arm/mach-bcmbca/bcm63138/Kconfig new file mode 100644 index 0000000000..a34888d231 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63138/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63138 + +config TARGET_BCM963138 + bool "Broadcom 63138 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63138" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63138/Makefile b/arch/arm/mach-bcmbca/bcm63138/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63138/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm63146/Kconfig b/arch/arm/mach-bcmbca/bcm63146/Kconfig new file mode 100644 index 0000000000..690cbf1eb2 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63146/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63146 + +config TARGET_BCM963146 + bool "Broadcom 63146 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63146" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63146/Makefile b/arch/arm/mach-bcmbca/bcm63146/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63146/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c new file mode 100644 index 0000000000..c6b7a54fbd --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm963146_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm963146_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm63148/Kconfig b/arch/arm/mach-bcmbca/bcm63148/Kconfig new file mode 100644 index 0000000000..f81504c25c --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63148/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63148 + +config TARGET_BCM963148 + bool "Broadcom 63148 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63148" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63148/Makefile b/arch/arm/mach-bcmbca/bcm63148/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63148/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm63158/Kconfig b/arch/arm/mach-bcmbca/bcm63158/Kconfig new file mode 100644 index 0000000000..b77444369e --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63158/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63158 + +config TARGET_BCM963158 + bool "Broadcom 63158 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63158" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63158/Makefile b/arch/arm/mach-bcmbca/bcm63158/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63158/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c new file mode 100644 index 0000000000..fe7efb30e2 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm963158_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm963158_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig new file mode 100644 index 0000000000..73ac46284b --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM63178 + +config TARGET_BCM963178 + bool "Broadcom 63178 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm63178" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm63178/Makefile b/arch/arm/mach-bcmbca/bcm63178/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm63178/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm6756/Kconfig b/arch/arm/mach-bcmbca/bcm6756/Kconfig new file mode 100644 index 0000000000..c83dcd0f3e --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6756/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6756 + +config TARGET_BCM96756 + bool "Broadcom 6756 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6756" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6756/Makefile b/arch/arm/mach-bcmbca/bcm6756/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6756/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm6813/Kconfig b/arch/arm/mach-bcmbca/bcm6813/Kconfig new file mode 100644 index 0000000000..25a4221bef --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6813/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6813 + +config TARGET_BCM96813 + bool "Broadcom 6813 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6813" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6813/Makefile b/arch/arm/mach-bcmbca/bcm6813/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6813/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c new file mode 100644 index 0000000000..eb736bf7d5 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm96813_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm96813_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig new file mode 100644 index 0000000000..229ab88dbb --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6846 + +config TARGET_BCM96846 + bool "Broadcom 6846 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6846" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6846/Makefile b/arch/arm/mach-bcmbca/bcm6846/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6846/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig new file mode 100644 index 0000000000..78087c7dd5 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6855 + +config TARGET_BCM96855 + bool "Broadcom 6855 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6855" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6855/Makefile b/arch/arm/mach-bcmbca/bcm6855/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6855/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o diff --git a/arch/arm/mach-bcmbca/bcm6856/Kconfig b/arch/arm/mach-bcmbca/bcm6856/Kconfig new file mode 100644 index 0000000000..6ac75cb840 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6856/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6856 + +config TARGET_BCM96856 + bool "Broadcom 6856 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6856" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6856/Makefile b/arch/arm/mach-bcmbca/bcm6856/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6856/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c new file mode 100644 index 0000000000..8e53b4929e --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm96856_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm96856_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig new file mode 100644 index 0000000000..a6504bae1f --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6858 + +config TARGET_BCM96858 + bool "Broadcom 6858 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6858" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6858/Makefile b/arch/arm/mach-bcmbca/bcm6858/Makefile new file mode 100644 index 0000000000..6262497703 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj-y += mmu_table.o diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c new file mode 100644 index 0000000000..898291075f --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 Broadcom Ltd. + */ +#include <common.h> +#include <asm/armv8/mmu.h> +#include <linux/sizes.h> + +static struct mm_region bcm96858_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 1UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { + /* SoC peripheral */ + .virt = 0xff800000UL, + .phys = 0xff800000UL, + .size = 0x100000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = bcm96858_mem_map; diff --git a/arch/arm/mach-bcmbca/bcm6878/Kconfig b/arch/arm/mach-bcmbca/bcm6878/Kconfig new file mode 100644 index 0000000000..43f8942c9b --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6878/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# + +if BCM6878 + +config TARGET_BCM96878 + bool "Broadcom 6878 Reference Board" + depends on ARCH_BCMBCA + +config SYS_SOC + default "bcm6878" + +source "board/broadcom/bcmbca/Kconfig" + +endif diff --git a/arch/arm/mach-bcmbca/bcm6878/Makefile b/arch/arm/mach-bcmbca/bcm6878/Makefile new file mode 100644 index 0000000000..beb979af75 --- /dev/null +++ b/arch/arm/mach-bcmbca/bcm6878/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2022 Broadcom Ltd +# +obj- += dummy.o |