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author | Tom Rini <trini@konsulko.com> | 2021-01-12 17:32:20 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-01-12 17:32:20 +0300 |
commit | 996f217ea368ecaef84863bb29699c0e185b9be7 (patch) | |
tree | 50e40e77c82d4543f68efd06778e4a58ef1c14e7 /arch/arm | |
parent | f71e574cf993bb89b07420ad90c209fd3f0a3f68 (diff) | |
parent | aeaef07c5124afbe848f727a24019cf432f5e011 (diff) | |
download | u-boot-996f217ea368ecaef84863bb29699c0e185b9be7.tar.xz |
Merge tag 'u-boot-atmel-2021.04-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel features for 2021.04 cycle
This feature set includes the new board SAMA7G5 EK, the new evaluation
kit for Microchip AT91 SAMA7G5 SoC . The current board support includes
two configurations for booting from eMMC (SDMMC0), SD-Card (SDMMC1), and
support for two Ethernet interfaces.
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/dts/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/dts/sama7g5.dtsi | 170 | ||||
-rw-r--r-- | arch/arm/dts/sama7g5ek-u-boot.dtsi | 65 | ||||
-rw-r--r-- | arch/arm/dts/sama7g5ek.dts | 202 | ||||
-rw-r--r-- | arch/arm/mach-at91/Kconfig | 8 |
5 files changed, 448 insertions, 0 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1a62e4c070..0f738c224f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -890,6 +890,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \ dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ omap5-uevm.dtb +dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ + sama7g5ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi new file mode 100644 index 0000000000..0cb6eaf5d0 --- /dev/null +++ b/arch/arm/dts/sama7g5.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev <eugen.hristev@microchip.com> + * Author: Claudiu Beznea <claudiu.beznea@microchip.com> + * + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clk/at91.h> + +/ { + model = "Microchip SAMA7G5 family SoC"; + compatible = "microchip,sama7g5"; + + clocks { + slow_rc_osc: slow_rc_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + + main_rc: main_rc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + A7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>; + clock-names = "cpu", "master", "xtal"; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pioA: pinctrl@e0014000 { + compatible = "atmel,sama5d2-gpio"; + reg = <0xe0014000 0x800>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + status = "okay"; + + pinctrl: pinctrl_default { + compatible = "microchip,sama7g5-pinctrl"; + }; + }; + + pmc: pmc@e0018000 { + compatible = "microchip,sama7g5-pmc"; + reg = <0xe0018000 0x200>; + #clock-cells = <2>; + clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>; + clock-names = "td_slck", "md_slck", "main_xtal", "main_rc"; + status = "okay"; + }; + + clk32: sckc@e001d050 { + compatible = "microchip,sam9x60-sckc"; + reg = <0xe001d050 0x4>; + clocks = <&slow_rc_osc>, <&slow_xtal>; + #clock-cells = <1>; + }; + + sdmmc0: sdio-host@e1204000 { + compatible = "microchip,sama7g5-sdhci"; + reg = <0xe1204000 0x300>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 80>; + assigned-clock-rates = <200000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + status = "disabled"; + }; + + sdmmc1: sdio-host@e1208000 { + compatible = "microchip,sama7g5-sdhci"; + reg = <0xe1208000 0x300>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 81>; + assigned-clock-rates = <200000000>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */ + status = "disabled"; + }; + + pit64b0: timer@e1800000 { + compatible = "microchip,sama7g5-pit64b"; + reg = <0xe1800000 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; + clock-names = "pclk", "gclk"; + status = "okay"; + }; + + flx1: flexcom@e181c000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe181c000 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe181c000 0x800>; + status = "disabled"; + + i2c1: i2c@600 { + compatible = "atmel,sama5d2-i2c"; + reg = <0x600 0x200>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; + }; + }; + + uart0: serial@e1824200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xe1824200 0x200>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; + clock-names = "usart"; + status = "disabled"; + }; + + gmac0: ethernet@e2800000 { + compatible = "cdns,sama7g5-gem"; + reg = <0xe2800000 0x4000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>; + clock-names = "hclk", "pclk", "tx_clk"; + assigned-clocks = <&pmc PMC_TYPE_GCK 51>; + assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */ + assigned-clock-rates = <125000000>; + status = "disabled"; + }; + + gmac1: ethernet@e2804000 { + compatible = "cdns,sama7g5-emac"; + reg = <0xe2804000 0x1000>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama7g5ek-u-boot.dtsi b/arch/arm/dts/sama7g5ek-u-boot.dtsi new file mode 100644 index 0000000000..5e1a0d53a5 --- /dev/null +++ b/arch/arm/dts/sama7g5ek-u-boot.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev <eugen.hristev@microchip.com> + * Author: Claudiu Beznea <claudiu.beznea@microchip.com> + * + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; + + ahb { + u-boot,dm-pre-reloc; + + apb { + u-boot,dm-pre-reloc; + }; + }; +}; + +&main_rc { + u-boot,dm-pre-reloc; +}; + +&main_xtal { + u-boot,dm-pre-reloc; +}; + +&pioA { + u-boot,dm-pre-reloc; + + pinctrl { + u-boot,dm-pre-reloc; + }; +}; + +&pinctrl_flx3_default { + u-boot,dm-pre-reloc; +}; + +&pit64b0 { + u-boot,dm-pre-reloc; +}; + +&pmc { + u-boot,dm-pre-reloc; +}; + +&slow_rc_osc { + u-boot,dm-pre-reloc; +}; + +&slow_xtal { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/sama7g5ek.dts new file mode 100644 index 0000000000..ff9c9eb45c --- /dev/null +++ b/arch/arm/dts/sama7g5ek.dts @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * sama7g5ek.dts - Device Tree file for SAMA7G5 EK + * SAMA7G5 Evaluation Kit + * + * Copyright (c) 2020, Microchip Technology Inc. + * 2020, Eugen Hristev <eugen.hristev@microchip.com> + * 2020, Claudiu Beznea <claudiu.beznea@microchip.com> + */ +/dts-v1/; +#include "sama7g5.dtsi" +#include "sama7g5-pinfunc.h" + +/ { + model = "Microchip SAMA7G5 Evaluation Kit"; + compatible = "microchip,sama7g5ek", "microchip,sama7g54", "microchip,sama7g5", "microchip,sama7"; + + aliases { + serial0 = &uart0; + i2c0 = &i2c1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + slow_xtal: slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal: main_xtal { + clock-frequency = <24000000>; + }; + }; + + ahb { + + apb { + sdmmc0: sdio-host@e1204000 { + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_data_default + &pinctrl_sdmmc0_ck_rstn_ds_cd_default>; + status = "okay"; + }; + + sdmmc1: sdio-host@e1208000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_data_default + &pinctrl_sdmmc1_ck_cd_rstn_vddsel_default>; + status = "okay"; + }; + + uart0: serial@e1824200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx3_default>; + status = "okay"; + }; + }; + }; +}; + +&flx1 { + atmel,flexcom-mode = <3>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx1_default>; + status = "okay"; + + eeprom@52 { + compatible = "microchip,24aa02e48"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "microchip,24aa02e48"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac0_default &pinctrl_gmac0_txc_default>; + phy-mode = "rgmii-id"; + status = "okay"; + + ethernet-phy@7 { + reg = <0x7>; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gmac1_default>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&pinctrl { + pinctrl_flx1_default: flx1_default { + pinmux = <PIN_PC9__FLEXCOM1_IO0>, + <PIN_PC10__FLEXCOM1_IO1>; + bias-disable; + }; + + pinctrl_flx3_default: flx3_default { + pinmux = <PIN_PD16__FLEXCOM3_IO0>, + <PIN_PD17__FLEXCOM3_IO1>; + bias-disable; + }; + + pinctrl_sdmmc0_cmd_data_default: sdmmc0_cmd_data_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA3__SDMMC0_DAT0>, + <PIN_PA4__SDMMC0_DAT1>, + <PIN_PA5__SDMMC0_DAT2>, + <PIN_PA6__SDMMC0_DAT3>, + <PIN_PA7__SDMMC0_DAT4>, + <PIN_PA8__SDMMC0_DAT5>, + <PIN_PA9__SDMMC0_DAT6>, + <PIN_PA10__SDMMC0_DAT7>; + bias-pull-up; + }; + + pinctrl_sdmmc0_ck_rstn_ds_cd_default: sdmmc0_ck_rstn_ds_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA2__SDMMC0_RSTN>, + <PIN_PA11__SDMMC0_DS>, + <PIN_PA14__SDMMC0_CD>; + bias-pull-up; + }; + + pinctrl_sdmmc1_cmd_data_default: sdmmc1_cmd_data_default { + pinmux = <PIN_PB29__SDMMC1_CMD>, + <PIN_PB31__SDMMC1_DAT0>, + <PIN_PC0__SDMMC1_DAT1>, + <PIN_PC1__SDMMC1_DAT2>, + <PIN_PC2__SDMMC1_DAT3>; + bias-pull-up; + }; + + pinctrl_sdmmc1_ck_cd_rstn_vddsel_default: sdmmc1_ck_cd_rstn_vddsel_default { + pinmux = <PIN_PB30__SDMMC1_CK>, + <PIN_PB28__SDMMC1_RSTN>, + <PIN_PC5__SDMMC1_1V8SEL>, + <PIN_PC4__SDMMC1_CD>; + bias-pull-up; + }; + + pinctrl_gmac0_default: gmac0_default { + pinmux = <PIN_PA16__G0_TX0>, + <PIN_PA17__G0_TX1>, + <PIN_PA26__G0_TX2>, + <PIN_PA27__G0_TX3>, + <PIN_PA19__G0_RX0>, + <PIN_PA20__G0_RX1>, + <PIN_PA28__G0_RX2>, + <PIN_PA29__G0_RX3>, + <PIN_PA15__G0_TXEN>, + <PIN_PA30__G0_RXCK>, + <PIN_PA18__G0_RXDV>, + <PIN_PA22__G0_MDC>, + <PIN_PA23__G0_MDIO>, + <PIN_PA25__G0_125CK>; + bias-disable; + }; + + pinctrl_gmac0_txc_default: gmac0_txc_default { + pinmux = <PIN_PA24__G0_TXCK>; + bias-pull-up; + }; + + pinctrl_gmac1_default: gmac1_default { + pinmux = <PIN_PD30__G1_TXCK>, + <PIN_PD22__G1_TX0>, + <PIN_PD23__G1_TX1>, + <PIN_PD21__G1_TXEN>, + <PIN_PD25__G1_RX0>, + <PIN_PD26__G1_RX1>, + <PIN_PD27__G1_RXER>, + <PIN_PD24__G1_RXDV>, + <PIN_PD28__G1_MDC>, + <PIN_PD29__G1_MDIO>; + bias-disable; + }; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index be1415f909..c78a308f48 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -265,6 +265,13 @@ config TARGET_CORVUS select SUPPORT_SPL imply CMD_DM +config TARGET_SAMA7G5EK + bool "SAMA7G5 EK board" + select SAMA7G5 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + + config TARGET_TAURUS bool "Support taurus" select AT91SAM9G20 @@ -327,6 +334,7 @@ source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" +source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" |