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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-02-14 20:35:34 +0300 |
|---|---|---|
| committer | Tom <twarren@nvidia.com> | 2023-02-23 22:55:37 +0300 |
| commit | 5668c75ce97d9209d4a0d193b16791a100cc99a8 (patch) | |
| tree | bf010da805d2bf3604bf0d7a21206aceb4439f4b /arch/arm | |
| parent | e7184debf4c2f35518811990473103793a1f639d (diff) | |
| download | u-boot-5668c75ce97d9209d4a0d193b16791a100cc99a8.tar.xz | |
board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-tegra/tegra30/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra30/cpu.c | 36 |
2 files changed, 0 insertions, 44 deletions
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig index 5619d1cd42..85b8ce294f 100644 --- a/arch/arm/mach-tegra/tegra30/Kconfig +++ b/arch/arm/mach-tegra/tegra30/Kconfig @@ -1,11 +1,5 @@ if TEGRA30 -config TEGRA_VDD_CORE_TPS62361B_SET3 - bool - -config TEGRA_VDD_CORE_TPS62366A_SET1 - bool - choice prompt "Tegra30 board select" optional @@ -17,12 +11,10 @@ config TARGET_APALIS_T30 config TARGET_BEAVER bool "NVIDIA Tegra30 Beaver evaluation board" select BOARD_LATE_INIT - select TEGRA_VDD_CORE_TPS62366A_SET1 config TARGET_CARDHU bool "NVIDIA Tegra30 Cardhu evaluation board" select BOARD_LATE_INIT - select TEGRA_VDD_CORE_TPS62361B_SET3 config TARGET_COLIBRI_T30 bool "Toradex Colibri T30 board" diff --git a/arch/arm/mach-tegra/tegra30/cpu.c b/arch/arm/mach-tegra/tegra30/cpu.c index 6ac45af51a..60bbf13ea5 100644 --- a/arch/arm/mach-tegra/tegra30/cpu.c +++ b/arch/arm/mach-tegra/tegra30/cpu.c @@ -15,20 +15,6 @@ #include <linux/delay.h> #include "../cpu.h" -#define TPS62366A_I2C_ADDR 0xC0 -#define TPS62366A_SET1_REG 0x01 -#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG) - -#define TPS62361B_I2C_ADDR 0xC0 -#define TPS62361B_SET3_REG 0x03 -#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG) - -#define TPS65911_I2C_ADDR 0x5A -#define TPS65911_VDDCTRL_OP_REG 0x28 -#define TPS65911_VDDCTRL_SR_REG 0x27 -#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG) -#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG) - /* In case this function is not defined */ __weak void pmic_enable_cpu_vdd(void) {} @@ -41,28 +27,6 @@ static void enable_cpu_power_rail(void) reg = readl(&pmc->pmc_cntrl); reg |= CPUPWRREQ_OE; writel(reg, &pmc->pmc_cntrl); - - /* Set VDD_CORE to 1.200V. */ -#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 - tegra_i2c_ll_write(TPS62366A_I2C_ADDR, - TPS62366A_SET1_DATA); -#endif -#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 - tegra_i2c_ll_write(TPS62361B_I2C_ADDR, - TPS62361B_SET3_DATA); -#endif - udelay(1000); - - /* - * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus. - * First set VDD to 1.0125V, then enable the VDD regulator. - */ - tegra_i2c_ll_write(TPS65911_I2C_ADDR, - TPS65911_VDDCTRL_OP_DATA); - udelay(1000); - tegra_i2c_ll_write(TPS65911_I2C_ADDR, - TPS65911_VDDCTRL_SR_DATA); - udelay(10 * 1000); } /** |