m68k: Remove M54451EVB board

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.  As this is also the last in family remove the related
support as well.

Cc: Angelo Durgehello <angelo.dureghello@timesys.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

4 files changed, 0 insertions, 289 deletions

diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 9deab51d07..9b3f9f0fe1 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -73,13 +73,6 @@ void cfspi_port_conf(void)
 {
 	gpio_t *gpio = (gpio_t *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	out_8(&gpio->par_dspi,
-	      GPIO_PAR_DSPI_SIN_SIN |
-	      GPIO_PAR_DSPI_SOUT_SOUT |
-	      GPIO_PAR_DSPI_SCK_SCK);
-#endif
-
 #ifdef CONFIG_MCF5441x
 	pm_t *pm = (pm_t *)MMAP_PM;
 
@@ -212,36 +205,6 @@ void cpu_init_f(void)
 #endif
 #endif		/* CONFIG_MCF5441x */
 
-#ifdef CONFIG_MCF5445x
-	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-
-	out_be32(&scm1->mpr, 0x77777777);
-	out_be32(&scm1->pacra, 0);
-	out_be32(&scm1->pacrb, 0);
-	out_be32(&scm1->pacrc, 0);
-	out_be32(&scm1->pacrd, 0);
-	out_be32(&scm1->pacre, 0);
-	out_be32(&scm1->pacrf, 0);
-	out_be32(&scm1->pacrg, 0);
-
-	/* FlexBus */
-	out_8(&gpio->par_be,
-		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
-		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
-	out_8(&gpio->par_fbctl,
-		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
-		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#ifdef CONFIG_CF_SPI
-	cfspi_port_conf();
-#endif
-
-#ifdef CONFIG_SYS_FSL_I2C
-	out_be16(&gpio->par_feci2c,
-		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-#endif		/* CONFIG_MCF5445x */
-
 	/* FlexBus Chipselect */
 	init_fbcs();
 
@@ -365,40 +328,6 @@ void uart_port_conf(int port)
 			GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
 		break;
 #endif
-#ifdef CONFIG_MCF5445x
-	case 0:
-		clrbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		setbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
-		break;
-	case 1:
-#ifdef CONFIG_SYS_UART1_PRI_GPIO
-		clrbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-		setbits_8(&gpio->par_uart,
-			GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
-#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
-		clrbits_be16(&gpio->par_ssi,
-			~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
-		setbits_be16(&gpio->par_ssi,
-			GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
-#endif
-		break;
-	case 2:
-#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
-		clrbits_8(&gpio->par_timer,
-			~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
-		setbits_8(&gpio->par_timer,
-			GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
-#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
-		clrbits_8(&gpio->par_timer,
-			~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
-		setbits_8(&gpio->par_timer,
-			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
-#endif
-		break;
-#endif	/* CONFIG_MCF5445x */
 	}
 }
 
@@ -411,46 +340,6 @@ int fecpin_setclear(fec_info_t *info, int setclear)
 	if (fec_get_base_addr(0, &fec0_base))
 		return -1;
 
-#ifdef CONFIG_MCF5445x
-	if (setclear) {
-#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
-		if (info->iobase == fec0_base)
-			setbits_be16(&gpio->par_feci2c,
-				GPIO_PAR_FECI2C_MDC0_MDC0 |
-				GPIO_PAR_FECI2C_MDIO0_MDIO0);
-		else
-			setbits_be16(&gpio->par_feci2c,
-				GPIO_PAR_FECI2C_MDC1_MDC1 |
-				GPIO_PAR_FECI2C_MDIO1_MDIO1);
-#else
-		setbits_be16(&gpio->par_feci2c,
-			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-#endif
-
-		if (info->iobase == fec0_base)
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
-		else
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
-	} else {
-		clrbits_be16(&gpio->par_feci2c,
-			GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
-
-		if (info->iobase == fec0_base) {
-#ifdef CONFIG_SYS_FEC_FULL_MII
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
-#else
-			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
-#endif
-		} else {
-#ifdef CONFIG_SYS_FEC_FULL_MII
-			setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
-#else
-			clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
-#endif
-		}
-	}
-#endif	/* CONFIG_MCF5445x */
-
 #ifdef CONFIG_MCF5441x
 	if (setclear) {
 		out_8(&gpio->par_fec, 0x03);
diff --git a/arch/m68k/cpu/mcf5445x/dspi.c b/arch/m68k/cpu/mcf5445x/dspi.c
index b0e2f2cb01..456af171a4 100644
--- a/arch/m68k/cpu/mcf5445x/dspi.c
+++ b/arch/m68k/cpu/mcf5445x/dspi.c
@@ -15,30 +15,6 @@ void dspi_chip_select(int cs)
 {
 	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
 #ifdef CONFIG_MCF5441x
 	switch (cs) {
 	case 0:
@@ -61,25 +37,6 @@ void dspi_chip_unselect(int cs)
 {
 	struct gpio *gpio = (struct gpio *)MMAP_GPIO;
 
-#ifdef CONFIG_MCF5445x
-	switch (cs) {
-	case 0:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
-		break;
-	case 1:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
-		break;
-	case 2:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
-		break;
-	case 3:
-		clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
-		break;
-	case 5:
-		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
-		break;
-	}
-#endif
 #ifdef CONFIG_MCF5441x
 	if (cs == 1)
 		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 4809bb49d1..eb73da68c6 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -42,11 +42,6 @@ void clock_enter_limp(int lpdiv)
 	/* Round divider down to nearest power of two */
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
-#ifdef CONFIG_MCF5445x
-	/* Apply the divider to the system clock */
-	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
-#endif
-
 	/* Enable Limp Mode */
 	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
 }
@@ -127,135 +122,12 @@ void setup_5441x_clocks(void)
 }
 #endif
 
-#ifdef CONFIG_MCF5445x
-void setup_5445x_clocks(void)
-{
-	ccm_t *ccm = (ccm_t *)MMAP_CCM;
-	pll_t *pll = (pll_t *)MMAP_PLL;
-	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
-	int pllmult_pci[] = { 12, 6, 16, 8 };
-	int vco = 0, temp, fbtemp, pcrvalue;
-	int *pPllmult = NULL;
-	u16 fbpll_mask;
-#ifdef CONFIG_PCI
-	int bPci;
-#endif
-
-	u8 bootmode;
-
-	/* To determine PCI is present or not */
-	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
-	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
-		pPllmult = &pllmult_pci[0];
-		fbpll_mask = 3;		/* 11b */
-#ifdef CONFIG_PCI
-		bPci = 1;
-#endif
-	} else {
-		pPllmult = &pllmult_nopci[0];
-		fbpll_mask = 7;		/* 111b */
-#ifdef CONFIG_PCI
-		gd->pci_clk = 0;
-		bPci = 0;
-#endif
-	}
-
-#ifdef CONFIG_M54451EVB
-	/* No external logic to read the bootmode, hard coded from built */
-#ifdef CONFIG_CF_SBF
-	bootmode = 3;
-#else
-	bootmode = 2;
-
-	/* default value is 16 mul, set to 20 mul */
-	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
-	out_be32(&pll->pcr, pcrvalue);
-	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
-		;
-#endif
-#endif
-
-	if (bootmode == 0) {
-		/* RCON mode */
-		vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
-
-		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
-			/* invaild range, re-set in PCR */
-			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-			int i, j, bus;
-
-			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
-			for (i = j; i < 0xFF; i++) {
-				vco = i * CONFIG_SYS_INPUT_CLKSRC;
-				if (vco >= CLOCK_PLL_FVCO_MIN) {
-					bus = vco / temp;
-					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
-						continue;
-					else
-						break;
-				}
-			}
-			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
-			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
-			pcrvalue |= ((i << 24) | fbtemp);
-
-			out_be32(&pll->pcr, pcrvalue);
-		}
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	} else if (bootmode == 2) {
-		/* Normal mode */
-		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
-			/* Default value */
-			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
-			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
-			out_be32(&pll->pcr, pcrvalue);
-			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		}
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	} else if (bootmode == 3) {
-		/* serial mode */
-		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		gd->arch.vco_clk = vco;	/* Vco clock */
-	}
-
-	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
-		/* Limp mode */
-	} else {
-		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
-
-		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
-		gd->cpu_clk = vco / temp;	/* cpu clock */
-
-		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
-		gd->bus_clk = vco / temp;	/* bus clock */
-
-		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
-		gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
-
-#ifdef CONFIG_PCI
-		if (bPci) {
-			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
-			gd->pci_clk = vco / temp;	/* PCI clock */
-		}
-#endif
-	}
-
-#ifdef CONFIG_SYS_I2C_FSL
-	gd->arch.i2c1_clk = gd->bus_clk;
-#endif
-}
-#endif
-
 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
 int get_clocks(void)
 {
 #ifdef CONFIG_MCF5441x
 	setup_5441x_clocks();
 #endif
-#ifdef CONFIG_MCF5445x
-	setup_5445x_clocks();
-#endif
 
 #ifdef CONFIG_SYS_FSL_I2C
 	gd->arch.i2c1_clk = gd->bus_clk;
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 80eb287151..7007d78c83 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -202,10 +202,6 @@ asm_dspi_init:
 	move.b	#0x80, (%a2)
 #endif
 
-#ifdef CONFIG_MCF5445x
-	move.l	#0xFC0A4063, %a0
-	move.b	#0x7F, (%a0)
-#endif
 	/* Configure DSPI module */
 	move.l	#0xFC05C000, %a0
 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
@@ -214,9 +210,6 @@ asm_dspi_init:
 #ifdef CONFIG_MCF5441x
 	move.l	#0x3E000016, (%a0)
 #endif
-#ifdef CONFIG_MCF5445x
-	move.l	#0x3E000011, (%a0)
-#endif
 
 	move.l	#0xFC05C034, %a2	/* dtfr */
 	move.l	#0xFC05C03B, %a3	/* drfr */