global: Finish CONFIG -> CFG migration

At this point, the remaining places where we have a symbol that is
defined as CONFIG_... are in fairly odd locations. While as much dead
code has been removed as possible, some of these locations are simply
less obvious at first. In other cases, this code is used, but was
defined in such a way as to have been missed by earlier checks.  Perform
a rename of all such remaining symbols to be CFG_... rather than
CONFIG_...

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

11 files changed, 217 insertions, 217 deletions

diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index b554c51fcb..331288e006 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -13,7 +13,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrl0, 0x1);
@@ -25,10 +25,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
 	clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
-	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
 #endif
diff --git a/arch/m68k/cpu/mcf52x2/interrupts.c b/arch/m68k/cpu/mcf52x2/interrupts.c
index 35ed1e7901..e8a1e132d2 100644
--- a/arch/m68k/cpu/mcf52x2/interrupts.c
+++ b/arch/m68k/cpu/mcf52x2/interrupts.c
@@ -37,10 +37,10 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE);
+	intctrl_t *intp = (intctrl_t *) (CFG_SYS_INTR_BASE);
 
 	clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK);
-	setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI);
+	setbits_be32(&intp->int_icr1, CFG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5272 */
@@ -49,7 +49,7 @@ void dtimer_intr_setup(void)
     defined(CONFIG_M5271) || defined(CONFIG_M5275)
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 #if defined(CONFIG_M5208)
@@ -66,11 +66,11 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
 	clrbits_be32(&intp->imrl0, 0x00000001);
-	clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
+	clrbits_be32(&intp->imrl0, CFG_SYS_TMRINTR_MASK);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5282 | CONFIG_M5271 | CONFIG_M5275 */
@@ -87,7 +87,7 @@ int interrupt_init(void)
 void dtimer_intr_setup(void)
 {
 	mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
-	mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI);
+	mbar_writeByte(MCFSIM_TIMER2ICR, CFG_SYS_TMRINTR_PRI);
 }
 #endif				/* CONFIG_MCFTMR */
 #endif				/* CONFIG_M5249 || CONFIG_M5253 */
diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c
index 2659e3478f..11686202dc 100644
--- a/arch/m68k/cpu/mcf530x/interrupts.c
+++ b/arch/m68k/cpu/mcf530x/interrupts.c
@@ -24,6 +24,6 @@ void dtimer_intr_setup(void)
 	/* clearing TIMER2 mask, so enabling the related interrupt */
 	out_be32(&icr->imr, in_be32(&icr->imr) & ~0x00000400);
 	/* set TIMER2 interrupt priority */
-	out_8(&icr->icr2, CONFIG_SYS_TMRINTR_PRI);
+	out_8(&icr->icr2, CFG_SYS_TMRINTR_PRI);
 }
 #endif
diff --git a/arch/m68k/cpu/mcf532x/interrupts.c b/arch/m68k/cpu/mcf532x/interrupts.c
index 8f2df452ba..64e04664a5 100644
--- a/arch/m68k/cpu/mcf532x/interrupts.c
+++ b/arch/m68k/cpu/mcf532x/interrupts.c
@@ -13,7 +13,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrh0, 0xffffffff);
@@ -26,9 +26,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
-	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
 }
 #endif
diff --git a/arch/m68k/cpu/mcf5445x/interrupts.c b/arch/m68k/cpu/mcf5445x/interrupts.c
index 5a6a88cd57..ea0cf87990 100644
--- a/arch/m68k/cpu/mcf5445x/interrupts.c
+++ b/arch/m68k/cpu/mcf5445x/interrupts.c
@@ -16,7 +16,7 @@
 
 int interrupt_init(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	setbits_be32(&intp->imrh0, 0xffffffff);
@@ -29,9 +29,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+	int0_t *intp = (int0_t *) (CFG_SYS_INTR_BASE);
 
-	out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
-	clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
+	out_8(&intp->icr0[CFG_SYS_TMRINTR_NO], CFG_SYS_TMRINTR_PRI);
+	clrbits_be32(&intp->imrh0, CFG_SYS_TMRINTR_MASK);
 }
 #endif
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index c05356fc93..8ed2b4dbab 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -11,21 +11,21 @@
 
 #if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
     defined(CONFIG_MCF52x2)
-#define CONFIG_CF_V2
+#define CFG_CF_V2
 #endif
 
 #if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || \
     defined(CONFIG_MCF5301x)
-#define CONFIG_CF_V3
+#define CFG_CF_V3
 #endif
 
 #if defined(CONFIG_MCF5441x)
-#define CONFIG_CF_V4E		/* Four Extra ACRn */
+#define CFG_CF_V4E		/* Four Extra ACRn */
 #endif
 
 /* ***** CACR ***** */
 /* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
 
 #define CF_CACR_CENB		(1 << 31)
 #define CF_CACR_CPD		(1 << 28)
@@ -46,10 +46,10 @@
 #define CF_CACR_EUSP		(1 << 4)
 #endif				/* CONFIG_MCF5249 || CONFIG_MCF5253 */
 
-#endif				/* CONFIG_CF_V2 */
+#endif				/* CFG_CF_V2 */
 
 /* V3 Core */
-#ifdef CONFIG_CF_V3
+#ifdef CFG_CF_V3
 
 #define CF_CACR_EC		(1 << 31)
 #define CF_CACR_ESB		(1 << 29)
@@ -65,10 +65,10 @@
 #define CF_CACR_DW		(1 << 5)
 #define CF_CACR_EUSP		(1 << 4)
 
-#endif				/* CONFIG_CF_V3 */
+#endif				/* CFG_CF_V3 */
 
 /* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 
 #define CF_CACR_DEC		(1 << 31)
 #define CF_CACR_DW		(1 << 30)
@@ -116,7 +116,7 @@
 #define CF_ACR_WP		(1 << 2)
 
 /* V2 Core */
-#ifdef CONFIG_CF_V2
+#ifdef CFG_CF_V2
 #define CF_ACR_CM		(1 << 6)
 #define CF_ACR_BWE		(1 << 5)
 #else
@@ -126,10 +126,10 @@
 #define CF_ACR_CM_CB		(1 << 5)
 #define CF_ACR_CM_P		(2 << 5)
 #define CF_ACR_CM_IP		(3 << 5)
-#endif				/* CONFIG_CF_V2 */
+#endif				/* CFG_CF_V2 */
 
 /* V4 Core */
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 #define CF_ACR_AMM		(1 << 10)
 #define CF_ACR_SP		(1 << 3)
 #endif				/* CONFIG_CF_V4 */
@@ -159,24 +159,24 @@
 #define CFG_SYS_CACHE_ACR2	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR3
-#define CONFIG_SYS_CACHE_ACR3	0
+#ifndef CFG_SYS_CACHE_ACR3
+#define CFG_SYS_CACHE_ACR3	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR4
-#define CONFIG_SYS_CACHE_ACR4	0
+#ifndef CFG_SYS_CACHE_ACR4
+#define CFG_SYS_CACHE_ACR4	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR5
-#define CONFIG_SYS_CACHE_ACR5	0
+#ifndef CFG_SYS_CACHE_ACR5
+#define CFG_SYS_CACHE_ACR5	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR6
-#define CONFIG_SYS_CACHE_ACR6	0
+#ifndef CFG_SYS_CACHE_ACR6
+#define CFG_SYS_CACHE_ACR6	0
 #endif
 
-#ifndef CONFIG_SYS_CACHE_ACR7
-#define CONFIG_SYS_CACHE_ACR7	0
+#ifndef CFG_SYS_CACHE_ACR7
+#define CFG_SYS_CACHE_ACR7	0
 #endif
 
 #define CF_ADDRMASK(x)		(((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
diff --git a/arch/m68k/include/asm/coldfire/intctrl.h b/arch/m68k/include/asm/coldfire/intctrl.h
index f7f0f07d30..3f7c458ef0 100644
--- a/arch/m68k/include/asm/coldfire/intctrl.h
+++ b/arch/m68k/include/asm/coldfire/intctrl.h
@@ -12,7 +12,7 @@
 #if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \
     defined(CONFIG_M5275) || defined(CONFIG_M5282) || \
     defined(CONFIG_M547x)
-#	define	CONFIG_SYS_CF_INTC_REG1
+#	define	CFG_SYS_CF_INTC_REG1
 #endif
 
 typedef struct int0_ctrl {
@@ -23,7 +23,7 @@ typedef struct int0_ctrl {
 	u32 imrl0;		/* 0x0C Mask Low */
 	u32 frch0;		/* 0x10 Force High */
 	u32 frcl0;		/* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 	u8 irlr;		/* 0x18 */
 	u8 iacklpr;		/* 0x19 */
 	u16 res1[19];		/* 0x1a - 0x3c */
@@ -64,7 +64,7 @@ typedef struct int1_ctrl {
 	u32 imrl1;		/* 0x0C Mask Low */
 	u32 frch1;		/* 0x10 Force High */
 	u32 frcl1;		/* 0x14 Force Low */
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 	u8 irlr;		/* 0x18 */
 	u8 iacklpr;		/* 0x19 */
 	u16 res1[19];		/* 0x1a - 0x3c */
@@ -192,7 +192,7 @@ typedef struct intgack_ctrl1 {
 #define INTC_IACKLPR_PRI(x)		((x) & 0x0F)
 #define INTC_IACKLPR_PRI_MASK		(0xF0)
 
-#if defined(CONFIG_SYS_CF_INTC_REG1)
+#if defined(CFG_SYS_CF_INTC_REG1)
 #define INTC_ICR_IL(x)			(((x) & 0x07) << 3)
 #define INTC_ICR_IL_MASK		(0xC7)
 #define INTC_ICR_IP(x)			((x) & 0x07)
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index 0c23744a86..8207c8d5b7 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -13,65 +13,65 @@
 #include <asm/immap_520x.h>
 #include <asm/m520x.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M520x */
 
 #ifdef CONFIG_M5235
 #include <asm/immap_5235.h>
 #include <asm/m5235.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5235 */
 
 #ifdef CONFIG_M5249
 #include <asm/immap_5249.h>
 #include <asm/m5249.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO		(31)
-#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRINTR_NO		(31)
+#define CFG_SYS_TMRINTR_MASK	(0x00000400)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5249 */
 
@@ -80,21 +80,21 @@
 #include <asm/m5249.h>
 #include <asm/m5253.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
-#define CONFIG_SYS_TMRINTR_NO		(27)
-#define CONFIG_SYS_TMRINTR_MASK	(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(mbar_readLong(MCFSIM_IPR))
+#define CFG_SYS_TMRINTR_NO		(27)
+#define CFG_SYS_TMRINTR_MASK	(0x00000400)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 2000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5253 */
 
@@ -102,43 +102,43 @@
 #include <asm/immap_5271.h>
 #include <asm/m5271.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5271 */
 
 #ifdef CONFIG_M5272
 #include <asm/immap_5272.h>
 #include <asm/m5272.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS		(64)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC)
+#define CFG_SYS_NUM_IRQS		(64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_TMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_TMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr)
-#define CONFIG_SYS_TMRINTR_NO		(INT_TMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
-#define CONFIG_SYS_TMRINTR_PEND	(0)
-#define CONFIG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_TMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_TMR3)
+#define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *)(CFG_SYS_INTR_BASE))->int_isr)
+#define CFG_SYS_TMRINTR_NO		(INT_TMR3)
+#define CFG_SYS_TMRINTR_MASK	(INT_ISR_INT24)
+#define CFG_SYS_TMRINTR_PEND	(0)
+#define CFG_SYS_TMRINTR_PRI		(INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5))
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5272 */
 
@@ -146,21 +146,21 @@
 #include <asm/immap_5275.h>
 #include <asm/m5275.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(192)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(192)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5275 */
 
@@ -168,21 +168,21 @@
 #include <asm/immap_5282.h>
 #include <asm/m5282.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x40))
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR3)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR3)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprl0)
+#define CFG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_MASK	(1 << INT0_LO_DTMR3)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)		/* Level must include inorder to work */
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif				/* CONFIG_M5282 */
 
@@ -190,23 +190,23 @@
 #include <asm/immap_5307.h>
 #include <asm/m5307.h>
 
-#define CONFIG_SYS_UART_BASE            (MMAP_UART0 + \
+#define CFG_SYS_UART_BASE            (MMAP_UART0 + \
 					(CFG_SYS_UART_PORT * 0x40))
-#define CONFIG_SYS_INTR_BASE            (MMAP_INTC)
-#define CONFIG_SYS_NUM_IRQS             (64)
+#define CFG_SYS_INTR_BASE            (MMAP_INTC)
+#define CFG_SYS_NUM_IRQS             (64)
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE          (MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE             (MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
-					(CONFIG_SYS_INTR_BASE))->ipr)
-#define CONFIG_SYS_TMRINTR_NO           (31)
-#define CONFIG_SYS_TMRINTR_MASK		(0x00000400)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
+#define CFG_SYS_UDELAY_BASE          (MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE             (MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(((volatile intctrl_t *) \
+					(CFG_SYS_INTR_BASE))->ipr)
+#define CFG_SYS_TMRINTR_NO           (31)
+#define CFG_SYS_TMRINTR_MASK		(0x00000400)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI          (MCFSIM_ICR_AUTOVEC | \
 					MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3)
-#define CONFIG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_TIMER_PRESCALER      (((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 #endif                          /* CONFIG_M5307 */
 
@@ -214,44 +214,44 @@
 #include <asm/immap_5301x.h>
 #include <asm/m5301x.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5301x */
 
 #if defined(CONFIG_M5329) || defined(CONFIG_M5373)
 #include <asm/immap_5329.h>
 #include <asm/m5329.h>
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x4000))
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
 #if defined(CONFIG_M54418)
@@ -259,10 +259,10 @@
 #include <asm/m5441x.h>
 
 #if (CFG_SYS_UART_PORT < 4)
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + \
 					(CFG_SYS_UART_PORT * 0x4000))
 #else
-#define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
+#define CFG_SYS_UART_BASE		(MMAP_UART4 + \
 					((CFG_SYS_UART_PORT - 4) * 0x4000))
 #endif
 
@@ -270,18 +270,18 @@
 
 /* Timer */
 #ifdef CONFIG_MCFTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
-#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
-#define CONFIG_SYS_TMRPND_REG	(((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
-#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
-#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(6)
-#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#define CFG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CFG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CFG_SYS_TMRPND_REG	(((int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CFG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CFG_SYS_TMRINTR_PEND		(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(6)
+#define CFG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(192)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(192)
 
 #endif				/* CONFIG_M54418 */
 
@@ -304,21 +304,21 @@
 #define FEC1_TX_INIT		31
 #endif
 
-#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
+#define CFG_SYS_UART_BASE		(MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100))
 
 #ifdef CONFIG_SLTTMR
-#define CONFIG_SYS_UDELAY_BASE		(MMAP_SLT1)
-#define CONFIG_SYS_TMR_BASE		(MMAP_SLT0)
-#define CONFIG_SYS_TMRPND_REG		(((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
-#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
-#define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
-#define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0x1E)
-#define CONFIG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
+#define CFG_SYS_UDELAY_BASE		(MMAP_SLT1)
+#define CFG_SYS_TMR_BASE		(MMAP_SLT0)
+#define CFG_SYS_TMRPND_REG		(((volatile int0_t *)(CFG_SYS_INTR_BASE))->iprh0)
+#define CFG_SYS_TMRINTR_NO		(INT0_HI_SLT0)
+#define CFG_SYS_TMRINTR_MASK	(INTC_IPRH_INT54)
+#define CFG_SYS_TMRINTR_PEND	(CFG_SYS_TMRINTR_MASK)
+#define CFG_SYS_TMRINTR_PRI		(0x1E)
+#define CFG_SYS_TIMER_PRESCALER	(gd->bus_clk / 1000000)
 #endif
 
-#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
-#define CONFIG_SYS_NUM_IRQS		(128)
+#define CFG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CFG_SYS_NUM_IRQS		(128)
 
 #ifdef CONFIG_PCI
 #define CFG_SYS_PCI_BAR0		(0x40000000)
diff --git a/arch/m68k/lib/cache.c b/arch/m68k/lib/cache.c
index 4ddda69f5a..57e5632fdb 100644
--- a/arch/m68k/lib/cache.c
+++ b/arch/m68k/lib/cache.c
@@ -33,12 +33,12 @@ void icache_enable(void)
 
 	*cf_icache_status = 1;
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr2"::"r"(CFG_SYS_CACHE_ACR2));
-	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
-#if defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
-	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(CFG_SYS_CACHE_ACR3));
+#if defined(CFG_CF_V4E)
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(CFG_SYS_CACHE_ACR6));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(CFG_SYS_CACHE_ACR7));
 #endif
 #else
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
@@ -55,10 +55,10 @@ void icache_disable(void)
 	*cf_icache_status = 0;
 	icache_invalid();
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
 #endif
@@ -88,12 +88,12 @@ void dcache_enable(void)
 	dcache_invalid();
 	*cf_dcache_status = 1;
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(CFG_SYS_CACHE_ACR0));
 	__asm__ __volatile__("movec %0, %%acr1"::"r"(CFG_SYS_CACHE_ACR1));
-#if defined(CONFIG_CF_V4E)
-	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
-	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+#if defined(CFG_CF_V4E)
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(CFG_SYS_CACHE_ACR4));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(CFG_SYS_CACHE_ACR5));
 #endif
 #endif
 
@@ -109,10 +109,10 @@ void dcache_disable(void)
 
 	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
 
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
-#if defined(CONFIG_CF_V4E)
+#if defined(CFG_CF_V4E)
 	__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
 	__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
 #endif
@@ -121,7 +121,7 @@ void dcache_disable(void)
 
 void dcache_invalid(void)
 {
-#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
+#if defined(CONFIG_CF_V4) || defined(CFG_CF_V4E)
 	u32 temp;
 
 	temp = CFG_SYS_DCACHE_INV;
diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c
index 1caef61d20..799daab561 100644
--- a/arch/m68k/lib/interrupts.c
+++ b/arch/m68k/lib/interrupts.c
@@ -14,7 +14,7 @@
 #include <asm/immap.h>
 #include <asm/ptrace.h>
 
-#define	NR_IRQS		(CONFIG_SYS_NUM_IRQS)
+#define	NR_IRQS		(CFG_SYS_NUM_IRQS)
 
 /*
  * Interrupt vector functions.
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index cd7437b3e2..2ce69088d9 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -21,23 +21,23 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static volatile ulong timestamp = 0;
 
-#ifndef CONFIG_SYS_WATCHDOG_FREQ
-#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#ifndef CFG_SYS_WATCHDOG_FREQ
+#define CFG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
 #endif
 
 #if defined(CONFIG_MCFTMR)
-#ifndef CONFIG_SYS_UDELAY_BASE
+#ifndef CFG_SYS_UDELAY_BASE
 #	error	"uDelay base not defined!"
 #endif
 
-#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
+#if !defined(CFG_SYS_TMR_BASE) || !defined(CFG_SYS_INTR_BASE) || !defined(CFG_SYS_TMRINTR_NO) || !defined(CFG_SYS_TMRINTR_MASK)
 #	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
 #endif
 extern void dtimer_intr_setup(void);
 
 void __udelay(unsigned long usec)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_UDELAY_BASE);
 	uint start, now, tmp;
 
 	while (usec > 0) {
@@ -52,7 +52,7 @@ void __udelay(unsigned long usec)
 		timerp->tcn = 0;
 		/* set period to 1 us */
 		timerp->tmr =
-		    CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
+		    CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR |
 		    DTIM_DTMR_RST_EN;
 
 		start = now = timerp->tcn;
@@ -63,15 +63,15 @@ void __udelay(unsigned long usec)
 
 void dtimer_interrupt(void *not_used)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
 
 	/* check for timer interrupt asserted */
-	if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
+	if ((CFG_SYS_TMRPND_REG & CFG_SYS_TMRINTR_MASK) == CFG_SYS_TMRINTR_PEND) {
 		timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF);
 		timestamp++;
 
 		#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
-		if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
+		if (CFG_SYS_WATCHDOG_FREQ && (timestamp % (CFG_SYS_WATCHDOG_FREQ)) == 0) {
 			schedule();
 		}
 		#endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
@@ -81,7 +81,7 @@ void dtimer_interrupt(void *not_used)
 
 int timer_init(void)
 {
-	volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE);
+	volatile dtmr_t *timerp = (dtmr_t *) (CFG_SYS_TMR_BASE);
 
 	timestamp = 0;
 
@@ -92,7 +92,7 @@ int timer_init(void)
 	timerp->tmr = DTIM_DTMR_RST_RST;
 
 	/* initialize and enable timer interrupt */
-	irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
+	irq_install_handler(CFG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
 
 	timerp->tcn = 0;
 	timerp->trr = 1000;	/* Interrupt every ms */
@@ -100,7 +100,7 @@ int timer_init(void)
 	dtimer_intr_setup();
 
 	/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
-	timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
+	timerp->tmr = CFG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 |
 	    DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN;
 
 	return 0;