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| author | Ovidiu Panait <ovpanait@gmail.com> | 2022-05-31 21:14:26 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-24 15:16:00 +0300 |
| commit | ef0a592ae8e2961519510f48ffe48b655b31610a (patch) | |
| tree | 2ca7f86b05e8c29a275ecceee3547b08083716b1 /arch/microblaze/cpu | |
| parent | 0ad71dc53af000609d4484a465e630e569e73d63 (diff) | |
| download | u-boot-ef0a592ae8e2961519510f48ffe48b655b31610a.tar.xz | |
microblaze: cache: improve dcache Kconfig options
Replace CONFIG_DCACHE with a Kconfig option more limited in scope -
XILINX_MICROBLAZE0_USE_WDC. It should be enabled if the processor supports
the "wdc" (Write to Data Cache) instruction. It will be used to guard
"wdc" invocations in microblaze cache code.
Also, drop all ifdefs around flush_cache() calls and only keep one
CONFIG_IS_ENABLED() guard within flush_cache() itself.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-5-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'arch/microblaze/cpu')
| -rw-r--r-- | arch/microblaze/cpu/cache.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index b6126de194..4e8e228a22 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -49,26 +49,31 @@ void dcache_enable(void) void dcache_disable(void) { -#ifdef CONFIG_DCACHE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#endif + MSRCLR(0x80); } void flush_cache(ulong addr, ulong size) { int i; - for (i = 0; i < size; i += 4) + for (i = 0; i < size; i += 4) { asm volatile ( #ifdef CONFIG_ICACHE "wic %0, r0;" #endif "nop;" -#ifdef CONFIG_DCACHE + : + : "r" (addr + i) + : "memory"); + + if (CONFIG_IS_ENABLED(XILINX_MICROBLAZE0_USE_WDC)) { + asm volatile ( "wdc.flush %0, r0;" -#endif "nop;" : : "r" (addr + i) : "memory"); + } + } } |