microblaze: cache: introduce cpuinfo structure

Introduce a minimal cpuinfo structure to hold cache related info. The
instruction/data cache size and cache line size are initialized early in
the boot to default Kconfig values. They will be overwritten with data
from PVR/dtb if the microblaze UCLASS_CPU driver is enabled.

The cpuinfo struct was placed in global_data to allow the microblaze
UCLASS_CPU driver to also run before relocation (initialized global data
should be read-only before relocation).

gd_cpuinfo() helper macro was added to avoid volatile
"-Wdiscarded-qualifiers" warnings when using the pointer directly.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-10-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/)

2 files changed, 40 insertions, 0 deletions

diff --git a/arch/microblaze/include/asm/cpuinfo.h b/arch/microblaze/include/asm/cpuinfo.h
new file mode 100644
index 0000000000..c27dd40af7
--- /dev/null
+++ b/arch/microblaze/include/asm/cpuinfo.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022, Ovidiu Panait <ovpanait@gmail.com>
+ */
+
+#ifndef __ASM_MICROBLAZE_CPUINFO_H
+#define __ASM_MICROBLAZE_CPUINFO_H
+
+/**
+ * struct microblaze_cpuinfo - CPU info for microblaze processor core.
+ *
+ * @icache_size: Size of instruction cache memory in bytes.
+ * @icache_line_length: Instruction cache line length in bytes.
+ * @dcache_size: Size of data cache memory in bytes.
+ * @dcache_line_length: Data cache line length in bytes.
+ */
+struct microblaze_cpuinfo {
+	u32 icache_size;
+	u32 icache_line_length;
+
+	u32 dcache_size;
+	u32 dcache_line_length;
+};
+
+/**
+ * microblaze_early_cpuinfo_init() - Initialize cpuinfo with default values.
+ *
+ * Initializes the global data cpuinfo structure with default values (cache
+ * size, cache line size, etc.). It is called very early in the boot process
+ * (start.S codepath right before the first cache flush call) to ensure that
+ * cache related operations are properly handled.
+ */
+void microblaze_early_cpuinfo_init(void);
+
+#endif	/* __ASM_MICROBLAZE_CPUINFO_H */
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index 05868ac4f5..93506dec89 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -8,12 +8,17 @@
 #ifndef	__ASM_GBL_DATA_H
 #define __ASM_GBL_DATA_H
 
+#include <asm/cpuinfo.h>
+
 /* Architecture-specific global data */
 struct arch_global_data {
+	struct microblaze_cpuinfo cpuinfo;
 };
 
 #include <asm-generic/global_data.h>
 
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r31")
 
+#define gd_cpuinfo()	((struct microblaze_cpuinfo *)&gd->arch.cpuinfo)
+
 #endif /* __ASM_GBL_DATA_H */