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| author | Ovidiu Panait <ovidiu.panait@windriver.com> | 2022-02-13 11:09:24 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2022-02-15 15:11:43 +0300 |
| commit | d1114b83405ceaccd46bce96001e6da4fab3ae40 (patch) | |
| tree | 8ff14c919f2cdf9625c279b1e914b9a19ff630bd /arch/microblaze | |
| parent | 339f489d524e8daa40a4ab0c64bfe65ef30f5fc6 (diff) | |
| download | u-boot-d1114b83405ceaccd46bce96001e6da4fab3ae40.tar.xz | |
microblaze: exception: fix unaligned data access register mask
The correct mask for getting the source/destination register from ESR in
the case of an unaligned access exception is 0x3E0. With this change, a
dummy unaligned store produces the expected info:
"""
>> swi r5, r0, 0x111
...
Hardware exception at 0x111 address
Unaligned data access exception
Unaligned word access
Unaligned store access
Register R5
Return address from exception 0x7f99dfc
### ERROR ### Please RESET the board ###
"""
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20220213080925.1548411-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/microblaze')
| -rw-r--r-- | arch/microblaze/cpu/exception.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/microblaze/cpu/exception.c b/arch/microblaze/cpu/exception.c index d37f04364a..d3640d3903 100644 --- a/arch/microblaze/cpu/exception.c +++ b/arch/microblaze/cpu/exception.c @@ -38,7 +38,7 @@ void _hw_exception_handler (void) printf("Unaligned %sword access\n", ((state & 0x800) ? "" : "half")); printf("Unaligned %s access\n", ((state & 0x400) ? "store" : "load")); - printf("Register R%x\n", (state & 0x3E) >> 5); + printf("Register R%x\n", (state & 0x3E0) >> 5); break; case 0x2: puts("Illegal op-code exception\n"); |