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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-07 20:02:05 +0300 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2018-09-22 22:02:03 +0300 |
| commit | 5ef337a0371e2b2c7905e7e20a38b6bfc80bb708 (patch) | |
| tree | 779823c3cff6633929662fa5ada75b773cffa7d9 /arch/mips/Kconfig | |
| parent | b838586086af3278bcaead3720c7a18813cf4619 (diff) | |
| download | u-boot-5ef337a0371e2b2c7905e7e20a38b6bfc80bb708.tar.xz | |
MIPS: cache: make index base address configurable
The index base address used for the cache initialisation is currently
hard-coded to CKSEG0. Make this value configurable if a MIPS system
needs to have a different address (e.g. in SRAM or ScratchPad RAM).
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips/Kconfig')
| -rw-r--r-- | arch/mips/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f71597f6da..30fb9bff74 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -219,6 +219,18 @@ config MIPS_CM_BASE the GCRs occupy a region of the physical address space which is otherwise unused, or at minimum that software doesn't need to access. +config MIPS_CACHE_INDEX_BASE + hex "Index base address for cache initialisation" + default 0x80000000 if CPU_MIPS32 + default 0xffffffff80000000 if CPU_MIPS64 + help + This is the base address for a memory block, which is used for + initialising the cache lines. This is also the base address of a memory + block which is used for loading and filling cache lines when + SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. + Normally this is CKSEG0. If the MIPS system needs to move this block + to some SRAM or ScratchPad RAM, adapt this option accordingly. + endmenu menu "OS boot interface" |