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authorTom Rini <trini@konsulko.com>2021-01-06 00:20:26 +0300
committerTom Rini <trini@konsulko.com>2021-01-06 00:20:26 +0300
commit720620e6916ba40b9a173bb07706d2c73f3c23e7 (patch)
treeb085821f1d1137d80e9bb73f405ea0680db338b9 /arch/mips/dts/mscc,ocelot.dtsi
parentc86b18074c9d40bfa63cda1068b6dfb810d4377d (diff)
parent62b07b5173e3d04fabfac42cf1f4779d021f94ad (diff)
downloadu-boot-720620e6916ba40b9a173bb07706d2c73f3c23e7.tar.xz
Merge tag 'v2021.01-rc5' into next
Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/mips/dts/mscc,ocelot.dtsi')
-rw-r--r--arch/mips/dts/mscc,ocelot.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 9a187b6e58..aeb4bf8f4b 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -100,7 +100,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "snps,dw-apb-ssi";
+ compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;