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authorSean Anderson <seanga2@gmail.com>2020-10-17 01:57:50 +0300
committerJagan Teki <jagan@amarulasolutions.com>2020-12-18 13:46:37 +0300
commit237e5880f8778ef2d26d029f53b57df56a72db4e (patch)
treeb6d716a0255591c19c5b59b80df55c156dd983d4 /arch/mips/dts
parentddd3450f399051478263e823f5f778745824bdb3 (diff)
downloadu-boot-237e5880f8778ef2d26d029f53b57df56a72db4e.tar.xz
spi: dw: Add SoC-specific compatible strings
This adds SoC-specific compatible strings to all users of the designware spi device. This will allow for the correct driver to be selected for each device. Where it is publicly documented, a compatible string for the specific device version has also been added. Devices without publicly-documented device versions include MSCC SoCs, and Arc Socs. All compatible strings except those for SoCFPGAs and some of the versioned strings have been taken from Linux. Since SSI_MAX_XFER_SIZE is determined at runtime, this is not strictly necessary. However, it is a good cleanup and brings things closer to Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/mips/dts')
-rw-r--r--arch/mips/dts/mscc,jr2.dtsi2
-rw-r--r--arch/mips/dts/mscc,ocelot.dtsi2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/dts/mscc,jr2.dtsi b/arch/mips/dts/mscc,jr2.dtsi
index 7f5a96fecd..c44e9a2b3a 100644
--- a/arch/mips/dts/mscc,jr2.dtsi
+++ b/arch/mips/dts/mscc,jr2.dtsi
@@ -94,7 +94,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "snps,dw-apb-ssi";
+ compatible = "mscc,jaguar2-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 9a187b6e58..aeb4bf8f4b 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -100,7 +100,7 @@
spi0: spi-master@101000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "snps,dw-apb-ssi";
+ compatible = "mscc,ocelot-spi", "snps,dw-apb-ssi";
reg = <0x101000 0x40>;
num-chipselect = <4>;
bus-num = <0>;