diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2019-09-25 12:45:22 +0300 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-10-25 18:20:44 +0300 |
| commit | 2d767a749725e485f62f7e97b7b309a903ac4e60 (patch) | |
| tree | 0b2edd70da5172f5d9f7d86c0c56a3f7a772dc90 /arch/mips/dts | |
| parent | 77ed3c42fee219fb50bca154b1ae36dbca8fc2e0 (diff) | |
| download | u-boot-2d767a749725e485f62f7e97b7b309a903ac4e60.tar.xz | |
dts: mtmips: add clock node for mt7628
This patch adds clkctrl node for mt7628 and adds clocks property for
some node.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'arch/mips/dts')
| -rw-r--r-- | arch/mips/dts/mt7628a.dtsi | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/arch/mips/dts/mt7628a.dtsi b/arch/mips/dts/mt7628a.dtsi index e9241a0737..6d2142f429 100644 --- a/arch/mips/dts/mt7628a.dtsi +++ b/arch/mips/dts/mt7628a.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/mt7628-clk.h> / { #address-cells = <1>; @@ -48,6 +49,14 @@ mask = <0x1>; }; + clkctrl: clkctrl@0x2c { + reg = <0x2c 0x8>, <0x10 0x4>; + reg-names = "syscfg0", "clkcfg"; + compatible = "mediatek,mt7628-clk"; + #clock-cells = <1>; + u-boot,dm-pre-reloc; + }; + watchdog: watchdog@100 { compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; reg = <0x100 0x30>; @@ -120,14 +129,14 @@ #address-cells = <1>; #size-cells = <0>; - clock-frequency = <200000000>; + clocks = <&clkctrl CLK_SPI>; }; uart0: uartlite@c00 { compatible = "mediatek,hsuart", "ns16550a"; reg = <0xc00 0x100>; - clock-frequency = <40000000>; + clocks = <&clkctrl CLK_UART0>; resets = <&resetc 12>; reset-names = "uart0"; @@ -142,7 +151,7 @@ compatible = "mediatek,hsuart", "ns16550a"; reg = <0xd00 0x100>; - clock-frequency = <40000000>; + clocks = <&clkctrl CLK_UART1>; resets = <&resetc 19>; reset-names = "uart1"; @@ -157,7 +166,7 @@ compatible = "mediatek,hsuart", "ns16550a"; reg = <0xe00 0x100>; - clock-frequency = <40000000>; + clocks = <&clkctrl CLK_UART2>; resets = <&resetc 20>; reset-names = "uart2"; @@ -184,8 +193,12 @@ #phy-cells = <0>; ralink,sysctl = <&sysc>; + resets = <&resetc 22 &resetc 25>; reset-names = "host", "device"; + + clocks = <&clkctrl CLK_UPHY>; + clock-names = "cg"; }; ehci@101c0000 { |