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authorStefan Roese <sr@denx.de>2020-07-30 14:56:15 +0300
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2020-08-03 22:11:41 +0300
commit7ab932825dd0ef363c2c8523e5b82836f1417dca (patch)
treea566e7389c687bb93af9766b729c0302f389029e /arch/mips/dts
parentfad5ec5ecd7b97325f5bf686a195760932af67b0 (diff)
downloadu-boot-7ab932825dd0ef363c2c8523e5b82836f1417dca.tar.xz
mips: octeon: dts: Add I2C DT nodes
Add I2C DT nodes to the Octeon dts / dtsi files. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/mips/dts')
-rw-r--r--arch/mips/dts/mrvl,cn73xx.dtsi20
-rw-r--r--arch/mips/dts/mrvl,octeon-ebb7304.dts10
2 files changed, 30 insertions, 0 deletions
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
index 8d32a49795..4c7b6e4160 100644
--- a/arch/mips/dts/mrvl,cn73xx.dtsi
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -86,5 +86,25 @@
reg-shift = <3>;
interrupts = <0x08040 4>;
};
+
+ i2c0: i2c@1180000001000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001000 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b000 1>, <0x0b001 1>, <0x0b002 1>;
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@1180000001200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cavium,octeon-7890-twsi";
+ reg = <0x11800 0x00001200 0x0 0x200>;
+ /* INT_ST, INT_TS, INT_CORE */
+ interrupts = <0x0b100 1>, <0x0b101 1>, <0x0b102 1>;
+ clock-frequency = <100000>;
+ };
};
};
diff --git a/arch/mips/dts/mrvl,octeon-ebb7304.dts b/arch/mips/dts/mrvl,octeon-ebb7304.dts
index 4e9c2de7d4..096e5c8f66 100644
--- a/arch/mips/dts/mrvl,octeon-ebb7304.dts
+++ b/arch/mips/dts/mrvl,octeon-ebb7304.dts
@@ -94,3 +94,13 @@
&uart0 {
clock-frequency = <1200000000>;
};
+
+&i2c0 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
+ clock-frequency = <100000>;
+};