diff options
| author | Stefan Roese <sr@denx.de> | 2020-09-02 09:29:02 +0300 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-10-07 21:25:56 +0300 |
| commit | a23c279059723aa7d01a35139f3f3cc941d73f30 (patch) | |
| tree | a63086f88d8512b875d600692e9d8ffdda520d13 /arch/mips/dts | |
| parent | 5dcf7cc590b348f1e730ec38242df64c179f10a8 (diff) | |
| download | u-boot-a23c279059723aa7d01a35139f3f3cc941d73f30.tar.xz | |
mips: octeon: dts: mrvl, cn73xx.dtsi: Add memory controller DT node
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/mips/dts')
| -rw-r--r-- | arch/mips/dts/mrvl,cn73xx.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi index f5ad4a6213..44a5a03014 100644 --- a/arch/mips/dts/mrvl,cn73xx.dtsi +++ b/arch/mips/dts/mrvl,cn73xx.dtsi @@ -72,6 +72,23 @@ <0x0300e 4>, <0x0300f 4>; }; + l2c: l2c@1180080000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7xxx-l2c"; + reg = <0x11800 0x80000000 0x0 0x01000000>; + u-boot,dm-pre-reloc; + }; + + lmc: lmc@1180088000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "cavium,octeon-7xxx-ddr4"; + reg = <0x11800 0x88000000 0x0 0x02000000>; // 2 IFs + u-boot,dm-pre-reloc; + l2c-handle = <&l2c>; + }; + reset: reset@1180006001600 { compatible = "mrvl,cn7xxx-rst"; reg = <0x11800 0x06001600 0x0 0x200>; |