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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-07-12 01:45:56 +0300 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2020-07-18 15:23:25 +0300 |
| commit | 60772433dd42987f3b965188d9577150084b8956 (patch) | |
| tree | c170a4737477d2b296d802438444e724dafe9ece /arch/mips | |
| parent | b55e07e5656c6838a14453705e90189908ad7d92 (diff) | |
| download | u-boot-60772433dd42987f3b965188d9577150084b8956.tar.xz | |
mips: refactor disabling of caches
Logically this code belongs to cache_init.S.
If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/cpu/start.S | 9 | ||||
| -rw-r--r-- | arch/mips/lib/cache_init.S | 6 |
2 files changed, 10 insertions, 5 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index c3d1e64c1c..a9f8743717 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -196,11 +196,10 @@ wr_done: mtc0 zero, CP0_COMPARE #ifndef CONFIG_SKIP_LOWLEVEL_INIT - mfc0 t0, CP0_CONFIG - and t0, t0, MIPS_CONF_IMPL - or t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG - ehb + /* Disable caches */ + PTR_LA t9, mips_cache_disable + jalr t9 + nop #endif #ifdef CONFIG_MIPS_CM diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 2233d27137..602741c65d 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -418,6 +418,12 @@ return: jr R_RETURN END(mips_cache_reset) +LEAF(mips_cache_disable) + move R_RETURN, ra + change_k0_cca_kseg1 CONF_CM_UNCACHED + jr R_RETURN + END(mips_cache_disable) + LEAF(change_k0_cca) mfc0 t0, CP0_CONFIG #if __mips_isa_rev >= 2 |