Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.10

cpu:
- Add driver for microblaze cpu

net:
- Add support for DM_ETH_PHY to AXI emac and emaclite

xilinx:
- Switch platforms to DM_ETH_PHY
- DT chagnes in ZynqMP and Zynq
- Enable support for SquashFS

zynqmp:
- Add support for KR260 boards
- Move BSS from address 0
- Move platform identification from board code to soc driver
- Improve zynqmp_psu_init_minimize

versal:
- Enable loading app at EL1

serial:
- Setup default address and clock rates for DEBUG uarts

pinctrl:
- Add support for tri state and output enable properties

relocate-rela:
- Clean relocate-rela implementation for ARM64
- Add support for Microblaze

microblaze:
- Add support for runtime relocation
- Rework cache handling (wiring, Kconfig) based on cpuinfo
- Remove interrupt support

timer:
- Extract axi timer driver from Microblaze to generic location

1 files changed, 0 insertions, 18 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9b62764f4f..2e0793a7a7 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -181,24 +181,6 @@ source "arch/mips/mach-octeon/Kconfig"
 if MIPS
 
 choice
-	prompt "Endianness selection"
-	help
-	  Some MIPS boards can be configured for either little or big endian
-	  byte order. These modes require different U-Boot images. In general there
-	  is one preferred byteorder for a particular system but some systems are
-	  just as commonly used in the one or the other endianness.
-
-config SYS_BIG_ENDIAN
-	bool "Big endian"
-	depends on SUPPORTS_BIG_ENDIAN
-
-config SYS_LITTLE_ENDIAN
-	bool "Little endian"
-	depends on SUPPORTS_LITTLE_ENDIAN
-
-endchoice
-
-choice
 	prompt "CPU selection"
 	default CPU_MIPS32_R2