diff options
| author | rick <rick@andestech.com> | 2017-04-17 09:41:58 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2017-05-22 09:05:33 +0300 |
| commit | 86132af799d51e8e94d87dc56a071f325f369e0c (patch) | |
| tree | eaa707979e38c41487e04cedf3f1685e15b72413 /arch/nds32/dts | |
| parent | a375ff8e14bea0a5cbfff99d6456aa8d9a3320ab (diff) | |
| download | u-boot-86132af799d51e8e94d87dc56a071f325f369e0c.tar.xz | |
nds32: Support AG101P serial DM.
Support AG101P serial device tree flow.
Signed-off-by: rick <rick@andestech.com>
Diffstat (limited to 'arch/nds32/dts')
| -rw-r--r-- | arch/nds32/dts/Makefile | 14 | ||||
| -rw-r--r-- | arch/nds32/dts/ag101p.dts | 49 |
2 files changed, 63 insertions, 0 deletions
diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile new file mode 100644 index 0000000000..2d8480bfea --- /dev/null +++ b/arch/nds32/dts/Makefile @@ -0,0 +1,14 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts new file mode 100644 index 0000000000..2baa3dc9ae --- /dev/null +++ b/arch/nds32/dts/ag101p.dts @@ -0,0 +1,49 @@ +/dts-v1/; +/ { + compatible = "nds32 ag101p"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@99600000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x99600000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + no-loopback-test = <1>; + }; + +}; |