diff options
| author | rick <rick@andestech.com> | 2017-05-18 09:37:53 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2017-05-22 09:05:46 +0300 |
| commit | b841b6e94662b3b21a56d6ecaab64dcdfb0d311c (patch) | |
| tree | 92847f53ffaeb104754e2940b32b981314627750 /arch/nds32/dts | |
| parent | f5076f869855045e527de7f1367c65f55a2b1448 (diff) | |
| download | u-boot-b841b6e94662b3b21a56d6ecaab64dcdfb0d311c.tar.xz | |
nds32: Support AE3XX platform.
Support Andestech AE3xx platform: serial, timer device tree flow.
Signed-off-by: rick <rick@andestech.com>
Diffstat (limited to 'arch/nds32/dts')
| -rw-r--r-- | arch/nds32/dts/Makefile | 1 | ||||
| -rw-r--r-- | arch/nds32/dts/ae3xx.dts | 65 |
2 files changed, 66 insertions, 0 deletions
diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile index 2d8480bfea..1d6b19579c 100644 --- a/arch/nds32/dts/Makefile +++ b/arch/nds32/dts/Makefile @@ -3,6 +3,7 @@ # dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb +dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts new file mode 100644 index 0000000000..9062760cb7 --- /dev/null +++ b/arch/nds32/dts/ae3xx.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <30000000>; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x88000000 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + +}; |