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authorTimur Tabi <timur@freescale.com>2012-08-14 10:47:21 +0400
committerAndy Fleming <afleming@freescale.com>2012-08-23 19:24:18 +0400
commit99abf7ded3b8daf82bdf1a60d1a92cb76c482c9a (patch)
tree7f5647a8cff29f9f99adb4c5005fbc7900b38388 /arch/powerpc/include/asm/immap_85xx.h
parenta2af6a7a84c32ee3c1500000d2a0238052a4f5e1 (diff)
downloadu-boot-99abf7ded3b8daf82bdf1a60d1a92cb76c482c9a.tar.xz
powerpc/85xx: add support for FM2 DTSEC5
Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/immap_85xx.h')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 83f8813db5..9bdfd97da2 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
#define FSL_CORENET_NUM_DEVDISR 2
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */