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| author | woonjiet.chong <woonjiet.chong@starfivetech.com> | 2021-09-02 06:23:13 +0300 |
|---|---|---|
| committer | Wei Liang Lim <weiliang.lim@starfivetech.com> | 2023-10-18 09:04:24 +0300 |
| commit | 1813fb1b66bdea66c7cf3073ab033ba5271888fb (patch) | |
| tree | 595602758d45e72147bd7848c54a3ff7f044b573 /arch/riscv/Kconfig | |
| parent | 4459ed60cb1e0562bc5b40405e2b4b9bbf766d57 (diff) | |
| download | u-boot-1813fb1b66bdea66c7cf3073ab033ba5271888fb.tar.xz | |
Enable SPL, OpenSBI and U-Boot proper boot flow for Dubhe FPGA
Diffstat (limited to 'arch/riscv/Kconfig')
| -rwxr-xr-x[-rw-r--r--] | arch/riscv/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 1c62c2345b..bfed12dbca 100644..100755 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,9 @@ config TARGET_SIPEED_MAIX config TARGET_OPENPITON_RISCV64 bool "Support RISC-V cores on OpenPiton SoC" +config TARGET_STARFIVE_DUBHE_FPGA + bool "Support StarFive Dubhe FPGA Board" + endchoice config SYS_ICACHE_OFF @@ -83,6 +86,7 @@ source "board/thead/th1520_lpi4a/Kconfig" source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" source "board/starfive/visionfive2/Kconfig" +source "board/starfive/dubhe_fpga/Kconfig" # platform-specific options below source "arch/riscv/cpu/andesv5/Kconfig" |