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| author | Sean Anderson <seanga2@gmail.com> | 2020-09-28 17:52:26 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-09-30 03:54:46 +0300 |
| commit | e5ca9a752399c2701cb71527d198bfa78268580d (patch) | |
| tree | 2e792a2bdf8bc6a50fc0ad4cb5b5f55f7ead0783 /arch/riscv/Kconfig | |
| parent | 15943bb558d2fef6ae6d2713e252db17754d207d (diff) | |
| download | u-boot-e5ca9a752399c2701cb71527d198bfa78268580d.tar.xz | |
riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a
DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously
implicitly depended on the CLINT to select REGMAP.
Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb),
the SiFive CLINT is part of the device tree passed in by qemu. This device
tree doesn't have a clocks or clock-frequency property on clint, so we need
to fall back on the timebase-frequency property. Perhaps in the future we
can get a clock-frequency property added to the qemu dtb.
Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller.
RISCV_SYSCON_CLINT is retained for this purpose.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d9155b9bab..aaa3b833a5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -155,10 +155,6 @@ config 64BIT config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. |