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| author | Sean Anderson <seanga2@gmail.com> | 2020-09-28 17:52:24 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-09-30 03:54:45 +0300 |
| commit | e86463f8e3a5006b43985c474ac74d0caabd0fd4 (patch) | |
| tree | 3d9c257c0d0245b69fae832ed66fbc2a49f35be3 /arch/riscv/Kconfig | |
| parent | 7616e3687e447b5a838f472afb5275fe6a841f5b (diff) | |
| download | u-boot-e86463f8e3a5006b43985c474ac74d0caabd0fd4.tar.xz | |
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
This converts the PLMT driver from the riscv-specific timer interface to be
a DM-based UCLASS_TIMER driver.
The clock-frequency/clocks properties are preferred over timebase-frequency
for two reasons. First, properties which affect a device should be located
near its binding in the device tree. Using timebase-frequency only really
makes sense when the cpu itself is the timer device. This is the case when
we read the time from a CSR, but not when there is a separate device.
Second, it lets the device use the clock subsystem which adds flexibility.
If the device is configured for a different clock speed, the timer can
adjust itself.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 21e6690f4d..d9155b9bab 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -177,10 +177,6 @@ config ANDES_PLIC config ANDES_PLMT bool depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. |