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| author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2019-08-21 22:14:43 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-08-26 11:07:42 +0300 |
| commit | fbfd92bf9bdc39d6537806ab58a83a48e5a2c004 (patch) | |
| tree | 8b4018a4e88bc57278bbc2d01b2cb3b137d55c88 /arch/riscv/Kconfig | |
| parent | b83edfbde9a845d47a2766f4677deb336abfa42a (diff) | |
| download | u-boot-fbfd92bf9bdc39d6537806ab58a83a48e5a2c004.tar.xz | |
riscv: add run mode configuration for SPL
U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.
Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'arch/riscv/Kconfig')
| -rw-r--r-- | arch/riscv/Kconfig | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8cfc7d0faa..b8d01ba8e1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -113,6 +113,23 @@ config RISCV_SMODE endchoice +choice + prompt "SPL Run Mode" + default SPL_RISCV_MMODE + depends on SPL + +config SPL_RISCV_MMODE + bool "Machine" + help + Choose this option to build U-Boot SPL for RISC-V M-Mode. + +config SPL_RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot SPL for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -132,34 +149,40 @@ config 64BIT config SIFIVE_CLINT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. config ANDES_PLIC bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. config ANDES_PLMT bool - depends on RISCV_MMODE + depends on RISCV_MMODE || SPL_RISCV_MMODE select REGMAP select SYSCON + select SPL_REGMAP if SPL + select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. config RISCV_RDTIME bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE help The provides the riscv_get_time() API that is implemented using the standard rdtime instruction. This is the case for S-mode U-Boot, and @@ -189,7 +212,7 @@ config NR_CPUS config SBI_IPI bool - default y if RISCV_SMODE + default y if RISCV_SMODE || SPL_RISCV_SMODE depends on SMP config XIP |