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author | Tom Rini <trini@konsulko.com> | 2023-02-28 01:28:21 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2023-02-28 01:28:21 +0300 |
commit | 5b197eee334bdf75cc9e9148161299679a5251ea (patch) | |
tree | edec3c21a01fb54d764d04caa2bd774823e76c2d /arch/riscv/cpu/andesv5/Kconfig | |
parent | 7a826ded4a0e409d73ff4a910685821d34f1b664 (diff) | |
parent | e8c80ac0f7a13bf0fc016ce324b870c0cff7a2b8 (diff) | |
download | u-boot-5b197eee334bdf75cc9e9148161299679a5251ea.tar.xz |
Merge tag 'v2023.04-rc3' into next
Prepare v2023.04-rc3
Diffstat (limited to 'arch/riscv/cpu/andesv5/Kconfig')
-rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig new file mode 100644 index 0000000000..82bb5a2a53 --- /dev/null +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -0,0 +1,15 @@ +config RISCV_NDS + bool + select ARCH_EARLY_INIT_R + imply CPU + imply CPU_RISCV + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) + imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE + imply SPL_CPU + imply SPL_OPENSBI + imply SPL_LOAD_FIT + help + Run U-Boot on AndeStar V5 platforms and use some specific features + which are provided by Andes Technology AndeStar V5 families. |