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| author | Samin Guo <samin.guo@starfivetech.com> | 2023-07-20 10:49:05 +0300 |
|---|---|---|
| committer | Samin Guo <samin.guo@starfivetech.com> | 2023-07-20 11:10:01 +0300 |
| commit | 7e61b32c84028f5f2df9b6d102cd3fe8f2577c3e (patch) | |
| tree | 41841cf81bbfa5aa2b7fdfd3e9b73dfce697c832 /arch/riscv/cpu/jh7110/spl.c | |
| parent | 24704a41a89784c2d25d1a76b2ed792f768d9fe2 (diff) | |
| download | u-boot-7e61b32c84028f5f2df9b6d102cd3fe8f2577c3e.tar.xz | |
board: starfive: evb: use dram_init in spl
dram_init call fdtdec_setup_mem_size_base, so starfive_ddr.c do not
need it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
Diffstat (limited to 'arch/riscv/cpu/jh7110/spl.c')
| -rw-r--r-- | arch/riscv/cpu/jh7110/spl.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 2a49fbee10..cba9874459 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <log.h> #include <asm/csr.h> +#include <init.h> #define CSR_U74_FEATURE_DISABLE 0x7c1 @@ -16,6 +17,11 @@ int spl_soc_init(void) int ret; struct udevice *dev; + /*read memory size info from eeprom and + *init gd->ram_size variable + */ + dram_init(); + /* DDR init */ ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { |