diff options
| author | Rick Chen <rick@andestech.com> | 2019-11-14 08:52:27 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-12-10 03:23:10 +0300 |
| commit | 444c46413fb691c7abbb2bec3ed498ab08fa36f8 (patch) | |
| tree | 6649bffbc1673264e11cd66d362c74e53508a289 /arch/riscv/cpu/start.S | |
| parent | 31dae22faa65534cb71631f6c74cbdcf4930a339 (diff) | |
| download | u-boot-444c46413fb691c7abbb2bec3ed498ab08fa36f8.tar.xz | |
riscv: Fix clear bss loop in the start-up code
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Diffstat (limited to 'arch/riscv/cpu/start.S')
| -rw-r--r-- | arch/riscv/cpu/start.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 0a2ce6d691..ee6d4717da 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -174,7 +174,7 @@ spl_clear_bss: spl_clear_bss_loop: SREG zero, 0(t0) addi t0, t0, REGBYTES - bne t0, t1, spl_clear_bss_loop + blt t0, t1, spl_clear_bss_loop spl_stack_gd_setup: jal spl_relocate_stack_gd @@ -324,7 +324,7 @@ clear_bss: clbss_l: SREG zero, 0(t0) /* clear loop... */ addi t0, t0, REGBYTES - bne t0, t1, clbss_l + blt t0, t1, clbss_l relocate_secondary_harts: #ifdef CONFIG_SMP |