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authorLukas Auer <lukas.auer@aisec.fraunhofer.de>2019-08-21 22:14:45 +0300
committerAndes <uboot@andestech.com>2019-08-26 11:07:42 +0300
commit8c59f2023cc8d4ab32b3988193ff2eb116df5995 (patch)
treef00b5a0faf61438352a4a8caab2d62a8f9539f2c /arch/riscv/cpu/start.S
parent5e30e45c83264841018dc8135034426fd0c0f857 (diff)
downloadu-boot-8c59f2023cc8d4ab32b3988193ff2eb116df5995.tar.xz
riscv: add SPL support
U-Boot SPL on the generic RISC-V CPU supports two boot flows, directly jumping to the image and via OpenSBI firmware. In the first case, both U-Boot SPL and proper must be compiled to run in the same privilege mode. Using OpenSBI firmware, U-Boot SPL must be compiled for machine mode and U-Boot proper for supervisor mode. To be able to use SPL, boards have to provide a supported SPL boot device. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
Diffstat (limited to 'arch/riscv/cpu/start.S')
-rw-r--r--arch/riscv/cpu/start.S23
1 files changed, 22 insertions, 1 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e82ee9e365..66c603906d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -75,7 +75,11 @@ _start:
*/
call_board_init_f:
li t0, -16
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+ li t1, CONFIG_SPL_STACK
+#else
li t1, CONFIG_SYS_INIT_SP_ADDR
+#endif
and sp, t1, t0 /* force 16 byte alignment */
call_board_init_f_0:
@@ -159,7 +163,24 @@ wait_for_gd_init:
mv a0, zero /* a0 <-- boot_flags = 0 */
la t5, board_init_f
- jr t5 /* jump to board_init_f() */
+ jalr t5 /* jump to board_init_f() */
+
+#ifdef CONFIG_SPL_BUILD
+spl_clear_bss:
+ la t0, __bss_start
+ la t1, __bss_end
+ beq t0, t1, spl_call_board_init_r
+
+spl_clear_bss_loop:
+ SREG zero, 0(t0)
+ addi t0, t0, REGBYTES
+ bne t0, t1, spl_clear_bss_loop
+
+spl_call_board_init_r:
+ mv a0, zero
+ mv a1, zero
+ jal board_init_r
+#endif
/*
* void relocate_code (addr_sp, gd, addr_moni)