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| author | Tom Rini <trini@konsulko.com> | 2023-07-24 17:58:07 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-24 17:58:07 +0300 |
| commit | 590a6cff974ab76df364cae2c793a89759cf78f3 (patch) | |
| tree | a1700bd3a54a61525667db85435d9939c0d05faa /arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | |
| parent | be71a05a417deb5fcea8e39e557f890626ab2352 (diff) | |
| parent | 6aabe229f8440c4960b904baf3aa33f692eea9a1 (diff) | |
| download | u-boot-590a6cff974ab76df364cae2c793a89759cf78f3.tar.xz | |
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Set up per-hart stack before any function call
- Sync visionfive2 board DTS with Linux
- Define cache line size for USB 3.0 driver for RISC-V CPU
Diffstat (limited to 'arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi')
| -rw-r--r-- | arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi index 710b082766..b90e7f8995 100644 --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi @@ -313,9 +313,9 @@ <&syscrg JH7110_SYSCLK_BUS_ROOT>, <&syscrg JH7110_SYSCLK_PERH_ROOT>, <&syscrg JH7110_SYSCLK_QSPI_REF>; - assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>, - <&syscrg JH7110_SYSCLK_PLL2_OUT>, - <&syscrg JH7110_SYSCLK_PLL2_OUT>, + assigned-clock-parents = <&pllclk JH7110_SYSCLK_PLL0_OUT>, + <&pllclk JH7110_SYSCLK_PLL2_OUT>, + <&pllclk JH7110_SYSCLK_PLL2_OUT>, <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>; assigned-clock-rates = <0>, <0>, <0>, <0>; }; |