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| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-05-29 09:44:51 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-03 10:09:06 +0300 |
| commit | 5ce50206ed24080707946849d3542534fadf8cbf (patch) | |
| tree | 291e2af14db172b24773bc1a8c7c2b699b263d29 /arch/riscv/dts | |
| parent | edf4fc2bafac18399d07152be51cb77d5d1bb3ac (diff) | |
| download | u-boot-5ce50206ed24080707946849d3542534fadf8cbf.tar.xz | |
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/dts')
| -rw-r--r-- | arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 35c153d851..afdb4f4402 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -87,3 +87,7 @@ assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; }; + +&l2cache { + status = "okay"; +}; |