diff options
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | 2020-05-29 09:44:51 +0300 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-07-03 10:09:06 +0300 |
| commit | 5ce50206ed24080707946849d3542534fadf8cbf (patch) | |
| tree | 291e2af14db172b24773bc1a8c7c2b699b263d29 /arch/riscv/include | |
| parent | edf4fc2bafac18399d07152be51cb77d5d1bb3ac (diff) | |
| download | u-boot-5ce50206ed24080707946849d3542534fadf8cbf.tar.xz | |
riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/arch-fu540/cache.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-fu540/cache.h b/arch/riscv/include/asm/arch-fu540/cache.h new file mode 100644 index 0000000000..135a17c679 --- /dev/null +++ b/arch/riscv/include/asm/arch-fu540/cache.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 SiFive, Inc. + * + * Authors: + * Pragnesh Patel <pragnesh.patel@sifve.com> + */ + +#ifndef _CACHE_SIFIVE_H +#define _CACHE_SIFIVE_H + +int cache_enable_ways(void); + +#endif /* _CACHE_SIFIVE_H */ |