diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-04-13 10:08:47 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:34 +0300 |
| commit | ef888a4df1dd200a95e8eb7aa90d0b08b89a1964 (patch) | |
| tree | 4805e0d21889a1d8c64945c4f5bad404a0869cc4 /arch/riscv/include | |
| parent | e9cef6c8ce31ff51099f23e2d628483cf762d728 (diff) | |
| download | u-boot-ef888a4df1dd200a95e8eb7aa90d0b08b89a1964.tar.xz | |
riscv:soc:jh7110: Add support jh7110 soc.
Add StarFive JH7110 soc to support RISC-V arch
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv/include')
| -rw-r--r-- | arch/riscv/include/asm/arch-jh7110/spl.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h new file mode 100644 index 0000000000..0756020809 --- /dev/null +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong <yanhong.wang@starfivetech.com> + * + */ + +#ifndef _SPL_STARFIVE_H +#define _SPL_STARFIVE_H + +int spl_soc_init(void); + +#endif /* _SPL_STARFIVE_H */ + |