clk:starfive-jh7110: Update pll0/pll1/pll2 clk

Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to  clk-jh7110.c

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

1 files changed, 0 insertions, 18 deletions

diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi
index 537cb3a054..6bffde586a 100644
--- a/arch/riscv/dts/jh7110_clk.dtsi
+++ b/arch/riscv/dts/jh7110_clk.dtsi
@@ -113,22 +113,4 @@
 		clock-frequency = <297000000>;
 	};
 	/* external clocks end */
-
-	pll0_out: pll0_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1250000000>;
-	};
-
-	pll1_out: pll1_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1066000000>;
-	};
-
-	pll2_out: pll2_out {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <1228800000>;
-	};
 };