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| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-15 10:27:22 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
| commit | 00018eb98a12f2ebbbd25fcca0d1262939ebc769 (patch) | |
| tree | 0a723d9657b66dca695f1e6be6fe1fc62fdd36de /arch/riscv | |
| parent | 845221c93ff817e702beeb571946b988092591b3 (diff) | |
| download | u-boot-00018eb98a12f2ebbbd25fcca0d1262939ebc769.tar.xz | |
riscv:starfive-jh7110: clear L2 LIM memory
Clear L2 LIM memory on StarFive JH7110, avoid some unexpect exception.
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/jh7110/spl.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index cb6ef2fda5..414938bce4 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -42,4 +42,18 @@ void harts_early_init(void) */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) csr_write(CSR_U74_FEATURE_DISABLE, 0); + +#ifdef CONFIG_SPL_BUILD + + /*clear L2 LIM memory + * set __bss_end to 0x81e0000 region to zero + */ + __asm__ __volatile__ ( + "la t1, __bss_end\n" + "li t2, 0x81e0000\n" + "spl_clear_l2im:\n" + "addi t1, t1, 8\n" + "sd zero, 0(t1)\n" + "blt t1, t2, spl_clear_l2im\n"); +#endif } |