diff options
author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-25 08:38:00 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:36 +0300 |
commit | 0b2572d9978f265b51a218f334434ab9fde41552 (patch) | |
tree | c62db17e443dc3e674a63e06ab1f5f17271aee84 /arch/riscv | |
parent | b239f16521b95137a46d6bfb59d8214da3f0620b (diff) | |
download | u-boot-0b2572d9978f265b51a218f334434ab9fde41552.tar.xz |
clk:starfive-jh7110: Update pll0/pll1/pll2 clk
Remove pll0/pll1/pll2 clk define from jh7110_clk.dts to clk-jh7110.c
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/dts/jh7110_clk.dtsi | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi index 537cb3a054..6bffde586a 100644 --- a/arch/riscv/dts/jh7110_clk.dtsi +++ b/arch/riscv/dts/jh7110_clk.dtsi @@ -113,22 +113,4 @@ clock-frequency = <297000000>; }; /* external clocks end */ - - pll0_out: pll0_out { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1250000000>; - }; - - pll1_out: pll1_out { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1066000000>; - }; - - pll2_out: pll2_out { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1228800000>; - }; }; |