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author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-26 06:16:21 +0300 |
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committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:36 +0300 |
commit | 16178e355d396994e63546d552a5c75e4aad71c0 (patch) | |
tree | 1238c29fec4e05df8680921e9ba8ded688809cbb /arch/riscv | |
parent | 5531f12c6efc79817914bf96f5b755840402e8c7 (diff) | |
download | u-boot-16178e355d396994e63546d552a5c75e4aad71c0.tar.xz |
SPL:starfive-jh7110: Modify the default division factor of sdcard clk
Modify the default division factor of sdcard clk to 4.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv')
-rwxr-xr-x | arch/riscv/include/asm/arch-jh7110/jh7110-regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h index 0672ee0d8d..a6a88c8581 100755 --- a/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h +++ b/arch/riscv/include/asm/arch-jh7110/jh7110-regs.h @@ -100,6 +100,10 @@ #define CLK_QSPI_REF_SW_SHIFT 24 #define CLK_QSPI_REF_SW_MASK 0x1000000U +#define CLK_SDIO0_SDCARD_OFFSET 0x174 +#define CLK_SDIO0_SDCARD_SHIFT 0 +#define CLK_SDIO0_SDCARD_MASK 0xFFFFFFU + #define PLL0_DACPD_SHIFT 0x18U #define PLL0_DACPD_MASK 0x1000000U #define PLL0_DSMPD_SHIFT 0x19U |