riscv:dts: add jh7110 support

Add dts support for jh7110. The starfive visionfive support is based on
jh7110 soc.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

6 files changed, 1341 insertions, 0 deletions

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b6e9166767..264639ad26 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE) += starfive_visionfive.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
new file mode 100644
index 0000000000..455da59622
--- /dev/null
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+#include <dt-bindings/reset/starfive-jh7110.h>
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+
+/ {
+	cpus: cpus {
+		u-boot,dm-spl;
+		timebase-frequency = <4000000>;
+
+		cpu0: cpu@0 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu0intctrl: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		cpu1: cpu@1 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu1intctrl: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		cpu2: cpu@2 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu2intctrl: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		cpu3: cpu@3 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu3intctrl: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+
+		cpu4: cpu@4 {
+			u-boot,dm-spl;
+			status = "okay";
+			cpu4intctrl: interrupt-controller {
+				u-boot,dm-spl;
+			};
+		};
+	};
+
+	soc {
+		u-boot,dm-spl;
+
+		clint: clint@2000000 {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <24000000>;
+	current-speed = <115200>;
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&sdio0 {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&sdio1 {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&rstgen {
+	status = "okay";
+	u-boot,dm-spl;
+};
+
+&nor_flash {
+	u-boot,dm-spl;
+};
+
+&clkgen {
+	u-boot,dm-spl;
+};
+
+&osc {
+	u-boot,dm-spl;
+};
+
+&gmac1_rmii_refin{
+	u-boot,dm-spl;
+};
+
+&stg_apb {
+	u-boot,dm-spl;
+};
+
+&gmac0_rmii_refin {
+	u-boot,dm-spl;
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
new file mode 100644
index 0000000000..f877cc627b
--- /dev/null
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -0,0 +1,984 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110_clk.dtsi"
+#include <dt-bindings/reset/starfive-jh7110.h>
+#include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+#include <dt-bindings/clock/starfive-jh7110-vout.h>
+
+/ {
+	compatible = "starfive,jh7110";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <0>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <8192>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <16384>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			riscv,isa = "rv64imac";
+			tlb-split;
+			status = "disabled";
+
+			cpu0intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <1>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+
+			cpu1intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <2>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+
+			cpu2intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <3>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+
+			cpu3intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+
+		cpu4: cpu@4 {
+			compatible = "sifive,u74-mc", "riscv";
+			reg = <4>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <64>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <40>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <64>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <40>;
+			mmu-type = "riscv,sv39";
+			next-level-cache = <&cachectrl>;
+			riscv,isa = "rv64imafdc";
+			tlb-split;
+			status = "okay";
+
+			cpu4intctrl: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		#clock-cells = <1>;
+		ranges;
+
+		cachectrl: cache-controller@2010000 {
+			compatible = "sifive,fu740-c000-ccache", "cache";
+			reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
+			reg-names = "control", "sideband";
+			interrupts = <1 3 4 2>;
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <2048>;
+			cache-size = <2097152>;
+			cache-unified;
+		};
+
+		clint: clint@2000000 {
+			compatible = "riscv,clint0";
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			reg-names = "control";
+			interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
+						&cpu1intctrl 3 &cpu1intctrl 7
+						&cpu2intctrl 3 &cpu2intctrl 7
+						&cpu3intctrl 3 &cpu3intctrl 7
+						&cpu4intctrl 3 &cpu4intctrl 7>;
+			#interrupt-cells = <1>;
+		};
+
+		plic: plic@c000000 {
+			compatible = "riscv,plic0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			reg-names = "control";
+			interrupts-extended = <&cpu0intctrl 11
+						&cpu1intctrl 11 &cpu1intctrl 9
+						&cpu2intctrl 11 &cpu2intctrl 9
+						&cpu3intctrl 11 &cpu3intctrl 9
+						&cpu4intctrl 11 &cpu4intctrl 9>;
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			riscv,max-priority = <7>;
+			riscv,ndev = <136>;
+		};
+
+		clkgen: clock-controller {
+			compatible = "starfive,jh7110-clkgen";
+			reg = <0x0 0x13020000 0x0 0x10000>,
+				<0x0 0x10230000 0x0 0x10000>,
+				<0x0 0x17000000 0x0 0x10000>;
+			reg-names = "sys", "stg", "aon";
+			clocks = <&osc>, <&gmac1_rmii_refin>,
+				<&gmac1_rgmii_rxin>,
+				<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+				<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+				<&tdm_ext>, <&mclk_ext>,
+				<&jtag_tck_inner>, <&bist_apb>,
+				<&stg_apb>, <&clk_rtc>,
+				<&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+			clock-names = "osc", "gmac1_rmii_refin",
+				"gmac1_rgmii_rxin",
+				"i2stx_bclk_ext", "i2stx_lrck_ext",
+				"i2srx_bclk_ext", "i2srx_lrck_ext",
+				"tdm_ext", "mclk_ext",
+				"jtag_tck_inner", "bist_apb",
+				"stg_apb", "clk_rtc",
+				"gmac0_rmii_refin", "gmac0_rgmii_rxin";
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		clkvout: clock-controller@295C0000 {
+			compatible = "starfive,jh7110-clk-vout";
+			reg = <0x0 0x295C0000 0x0 0x10000>;
+			reg-names = "vout";
+			clocks = <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
+				<&clkgen JH7110_VOUT_TOP_CLK_MIPIPHY_REF>,
+				<&clkgen JH7110_VOUT_TOP_CLK_MIPIPHY_REF>;
+			clock-names = "hdmitx0_pixelclk",
+				"mipitx_dphy_rxesc",
+				"mipitx_dphy_txbytehs";
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		clkisp: clock-controller@19810000 {
+			compatible = "starfive,jh7110-clk-isp";
+			reg = <0x0 0x19810000 0x0 0x10000>;
+			reg-names = "isp";
+			#clock-cells = <1>;
+			status = "disabled";
+		};
+
+		qspi: qspi@13010000 {
+			compatible = "cadence,qspi","cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x13010000 0x0 0x10000
+				0x0 0x21000000 0x0 0x400000>;
+			clocks = <&clkgen JH7110_QSPI_CLK_REF>;
+			clock-names = "clk_ref";
+			resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
+					<&rstgen RSTN_U0_CDNS_QSPI_AHB>,
+					<&rstgen RSTN_U0_CDNS_QSPI_REF>;
+			resets-names = "rst_apb", "rst_ahb", "rst_ref";
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			spi-max-frequency = <250000000>;
+
+			nor_flash: nor-flash@0 {
+				compatible = "jedec,spi-nor";
+				reg=<0>;
+				spi-max-frequency = <100000000>;
+				cdns,tshsl-ns = <1>;
+				cdns,tsd2d-ns = <1>;
+				cdns,tchsh-ns = <1>;
+				cdns,tslch-ns = <1>;
+			};
+		};
+
+		otp: otp@17050000 {
+			compatible = "starfive,jh7110-otp";
+			reg = <0x0 0x17050000 0x0 0x10000>;
+			clock-frequency = <4000000>;
+			clocks = <&clkgen JH7110_OTPC_CLK_APB>;
+			clock-names = "apb";
+		};
+
+		USB30: usb@10100000 {
+			compatible = "cdns,usb3";
+			reg = <0x0 0x10100000 0x0 0x10000>,
+				<0x0 0x10110000 0x0 0x10000>,
+				<0x0 0x10120000 0x0 0x10000>;
+			reg-names = "otg", "xhci", "dev";
+			phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+			clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
+				<&clkgen JH7110_USB0_CLK_LPM>,
+				<&clkgen JH7110_USB0_CLK_STB>,
+				<&clkgen JH7110_USB0_CLK_USB_APB>,
+				<&clkgen JH7110_USB0_CLK_AXI>,
+				<&clkgen JH7110_USB0_CLK_UTMI_APB>;
+			clock-names = "app","lpm","stb","apb","axi","utmi";
+			resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+					<&rstgen RSTN_U0_CDN_USB_APB>,
+					<&rstgen RSTN_U0_CDN_USB_AXI>,
+					<&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+			reset-names = "rst_pweup","rst_apb","rst_axi","rst_utmi";
+		};
+
+		timer: timer@13050000 {
+			compatible = "starfive,si5-timers";
+			reg = <0x0 0x13050000 0x0 0x10000>;
+			interrupts = <69>, <70>, <71> ,<72>;
+			interrupt-names = "timer0", "timer1", "timer2", "timer3";
+			clock-frequency = <2000000>;
+			status = "disabled";
+		};
+
+		wdog: wdog@13070000 {
+			compatible = "starfive,dskit-wdt";
+			reg = <0x0 0x13070000 0x0 0x10000>;
+			interrupts = <68>;
+			interrupt-names = "wdog";
+			clock-frequency = <2000000>;
+			timeout-sec = <15>;
+			status = "okay";
+		};
+
+		rtc: rtc@17040000 {
+			compatible = "starfive,rtc_hms";
+			reg = <0x0 0x17040000 0x0 0x10000>;
+			interrupts = <10>, <11>, <12>;
+			interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
+			clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>, <&clkgen JH7110_RTC_HMS_CLK_CAL>;
+			clock-names = "pclk", "cal_clk";
+			rtc,cal-clock-freq = <1000000>;
+			status = "okay";
+		};
+
+		pmu: pmu@17030000 {
+			compatible = "starfive,jh7110-pmu";
+			reg = <0x0 0x17030000 0x0 0x10000>;
+			interrupts = <111>;
+			status = "okay";
+		};
+
+		uart0: serial@10000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10000000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART0_CLK_CORE>,
+					<&clkgen JH7110_UART0_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <32>;
+			status = "disabled";
+		};
+
+		uart1: serial@10010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10010000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART1_CLK_CORE>,
+					<&clkgen JH7110_UART1_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <33>;
+			status = "disabled";
+		};
+
+		uart2: serial@10020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x10020000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART2_CLK_CORE>,
+					<&clkgen JH7110_UART2_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <34>;
+			status = "disabled";
+		};
+
+		uart3: serial@12000000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12000000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART3_CLK_CORE>,
+					<&clkgen JH7110_UART3_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <45>;
+			status = "disabled";
+		};
+
+		uart4: serial@12010000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12010000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART4_CLK_CORE>,
+					<&clkgen JH7110_UART4_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <46>;
+			status = "disabled";
+		};
+
+		uart5: serial@12020000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x12020000 0x0 0x10000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			clocks = <&clkgen JH7110_UART5_CLK_CORE>,
+					<&clkgen JH7110_UART5_CLK_APB>;
+			clock-names = "baudclk", "apb_pclk";
+			interrupts = <47>;
+			status = "disabled";
+		};
+
+		dma: dma-controller@16050000 {
+			compatible = "starfive,axi-dma";
+			reg = <0x0 0x16050000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_DMA1P_CLK_AHB>, <&clkgen JH7110_DMA1P_CLK_AXI>;
+			clock-names = "core-clk", "cfgr-clk";
+			interrupts = <73>;
+			#dma-cells = <2>;
+			dma-channels = <4>;
+			snps,dma-masters = <1>;
+			snps,data-width = <3>;
+			snps,num-hs-if = <56>;
+			snps,block-size = <65536 65536 65536 65536>;
+			snps,priority = <0 1 2 3>;
+			snps,axi-max-burst-len = <16>;
+			status = "disabled";
+		};
+
+		gpio: gpio@13040000 {
+			compatible = "starfive_jh7110-sys-pinctrl";
+			reg = <0x0 0x13040000 0x0 0x10000>;
+			reg-names = "control";
+			interrupts = <91>;
+			interrupt-controller;
+			#gpio-cells = <2>;
+			ngpios = <64>;
+			status = "okay";
+		};
+
+		gpioa: gpio@17020000 {
+			compatible = "starfive_jh7110-aon-pinctrl";
+			reg = <0x0 0x17020000 0x0 0x10000>;
+			reg-names = "control";
+			interrupts = <90>;
+			interrupt-controller;
+			#gpio-cells = <2>;
+			ngpios = <4>;
+			status = "okay";
+		};
+
+		trng: trng@1600C000 {
+			compatible = "starfive,trng";
+			reg = <0x0 0x1600C000 0x0 0x4000>;
+			clocks = <&clkgen JH7110_APB12>;
+			interrupts = <30>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@12060000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12060000 0x0 0x10000>;
+			interrupts = <51>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@10030000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10030000 0x0 0x10000>;
+			interrupts = <35>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@10040000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x10040000 0x0 0x10000>;
+			interrupts = <36>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		sdio0: sdio0@16010000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x0 0x16010000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
+					<&clkgen JH7110_SDIO0_CLK_SDCARD>;
+			clock-names = "biu","ciu";
+			interrupts = <74>;
+			fifo-depth = <32>;
+			fifo-watermark-aligned;
+			data-addr = <0>;
+			status = "disabled";
+		};
+
+		sdio1: sdio1@16020000 {
+			compatible = "snps,dw-mshc";
+			reg = <0x0 0x16020000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
+					<&clkgen JH7110_SDIO1_CLK_SDCARD>;
+			clock-names = "biu","ciu";
+			interrupts = <75>;
+			fifo-depth = <32>;
+			fifo-watermark-aligned;
+			data-addr = <0>;
+			status = "disabled";
+		};
+
+		vin_sysctl: vin_sysctl@19800000 {
+			compatible = "starfive,stf-vin";
+			reg = <0x0 0x19800000 0x0 0x10000>,
+				<0x0 0x19810000 0x0 0x10000>,
+				<0x0 0x19820000 0x0 0x10000>,
+				<0x0 0x19830000 0x0 0x10000>,
+				<0x0 0x19840000 0x0 0x10000>,
+				<0x0 0x19870000 0x0 0x30000>,
+				<0x0 0x198a0000 0x0 0x30000>,
+				<0x0 0x11800000 0x0 0x10000>,
+				<0x0 0x11840000 0x0 0x10000>,
+				<0x0 0x11858000 0x0 0x10000>,
+				<0x0 0x17030000 0x0 0x10000>,
+				<0x0 0x13020000 0x0 0x10000>;
+			reg-names = "mipi0", "vclk", "vrst", "mipi1",
+				"sctrl", "isp0", "isp1", "tclk", "trst",
+				"iopad", "pmu", "syscrg";
+			interrupts = <92 87 86>;
+			status = "disabled";
+		};
+
+		jpu: jpu@11900000 {
+			compatible = "starfive,jpu";
+			reg = <0x0 0x13090000 0x0 0x300>;
+			clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
+					<&clkgen JH7110_CODAJ12_CLK_CORE>,
+					<&clkgen JH7110_CODAJ12_CLK_APB>;
+			clock-names = "axi_clk", "core_clk", "apb_clk";
+			resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
+				<&rstgen RSTN_U0_CODAJ12_CORE>,
+				<&rstgen RSTN_U0_CODAJ12_APB>;
+			reset-names = "rst_axi",
+				"rst_core",
+				"rst_apb";
+			interrupts = <14>;
+			status = "disabled";
+		};
+
+		vpu_dec: vpu_dec@130A0000 {
+			compatible = "starfive,vdec";
+			reg = <0x0 0x130A0000 0x0 0x10000>;
+			interrupts = <13>;
+			clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
+				<&clkgen JH7110_WAVE511_CLK_BPU>,
+				<&clkgen JH7110_WAVE511_CLK_VCE>,
+				<&clkgen JH7110_WAVE511_CLK_APB>,
+				<&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
+			clock-names = "axi_clk",
+				"bpu_clk",
+				"vce_clk",
+				"apb_clk",
+				"noc_bus";
+			resets = <&rstgen RSTN_U0_WAVE511_AXI>,
+				<&rstgen RSTN_U0_WAVE511_BPU>,
+				<&rstgen RSTN_U0_WAVE511_VCE>,
+				<&rstgen RSTN_U0_WAVE511_APB>,
+				<&rstgen RSTN_U0_AXIMEM_128B_AXI>;
+			reset-names = "rst_axi",
+				"rst_bpu",
+				"rst_vce",
+				"rst_apb",
+				"rst_sram";
+			starfive,vdec_noc_ctrl;
+			status = "disabled";
+		};
+
+		vpu_enc: vpu_enc@130B0000 {
+			compatible = "starfive,venc";
+			reg = <0x0 0x130B0000 0x0 0x10000>;
+			interrupts = <15>;
+			clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
+				<&clkgen JH7110_WAVE420L_CLK_BPU>,
+				<&clkgen JH7110_WAVE420L_CLK_VCE>,
+				<&clkgen JH7110_WAVE420L_CLK_APB>,
+				<&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
+			clock-names = "axi_clk",
+				"bpu_clk",
+				"vce_clk",
+				"apb_clk",
+				"noc_bus";
+			resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
+				<&rstgen RSTN_U0_WAVE420L_BPU>,
+				<&rstgen RSTN_U0_WAVE420L_VCE>,
+				<&rstgen RSTN_U0_WAVE420L_APB>,
+				<&rstgen RSTN_U1_AXIMEM_128B_AXI>;
+			reset-names = "rst_axi",
+				"rst_bpu",
+				"rst_vce",
+				"rst_apb",
+				"rst_sram";
+			starfive,venc_noc_ctrl;
+			status = "disabled";
+		};
+
+		rstgen: reset-controller {
+			compatible = "starfive,jh7110-reset";
+			reg = <0x0 0x13020000 0x0 0x10000>,
+				<0x0 0x10230000 0x0 0x10000>,
+				<0x0 0x17000000 0x0 0x10000>,
+				<0x0 0x19810000 0x0 0x10000>,
+				<0x0 0x295C0000 0x0 0x10000>;
+			reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
+			#reset-cells = <1>;
+			status = "okay";
+		};
+
+		stmmac_axi_setup: stmmac-axi-config {
+			snps,wr_osr_lmt = <0xf>;
+			snps,rd_osr_lmt = <0xf>;
+			snps,blen = <256 128 64 32 0 0 0>;
+		};
+
+		gmac0: gmac0@16030000 {
+			compatible = "starfive,jh7110-eqos-5.20";
+			reg = <0x0 0x16030000 0x0 0x10000>;
+			clock-names = "gtx",
+				"tx",
+				"ptp_ref",
+				"stmmaceth",
+				"pclk";
+			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
+				<&clkgen JH7110_U0_GMAC5_CLK_TX>,
+				<&clkgen JH7110_GMAC0_PTP>,
+				<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
+				<&clkgen JH7110_U0_GMAC5_CLK_AXI>;
+			resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
+					<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
+			reset-names = "ahb", "stmmaceth";
+			interrupts = <7>, <6>, <5> ;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+			max-frame-size = <9000>;
+			phy-mode = "rgmii-id";
+			snps,multicast-filter-bins = <256>;
+			snps,perfect-filter-entries = <128>;
+			rx-fifo-depth = <262144>;
+			tx-fifo-depth = <131072>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,tso;
+			snps,en-tx-lpi-clockgating;
+			snps,en-lpi;
+			snps,write-requests = <2>;
+			snps,read-requests = <16>;
+			snps,burst-map = <0x7>;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			status = "disabled";
+		};
+
+		gmac1: gmac01@16040000 {
+			compatible = "starfive,jh7110-eqos-5.20";
+			reg = <0x0 0x16040000 0x0 0x10000>;
+			clock-names = "gtx",
+				"tx",
+				"ptp_ref",
+				"stmmaceth",
+				"pclk";
+			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
+				<&clkgen JH7110_GMAC5_CLK_TX>,
+				<&clkgen JH7110_GMAC5_CLK_PTP>,
+				<&clkgen JH7110_GMAC5_CLK_AHB>,
+				<&clkgen JH7110_GMAC5_CLK_AXI>;
+			resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
+					<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
+			reset-names = "ahb", "stmmaceth";
+			interrupts = <78>, <77>, <76> ;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+			max-frame-size = <9000>;
+			phy-mode = "rgmii-id";
+			snps,multicast-filter-bins = <256>;
+			snps,perfect-filter-entries = <128>;
+			rx-fifo-depth = <262144>;
+			tx-fifo-depth = <131072>;
+			snps,fixed-burst;
+			snps,no-pbl-x8;
+			snps,force_thresh_dma_mode;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,tso;
+			snps,en-tx-lpi-clockgating;
+			snps,en-lpi;
+			snps,write-requests = <2>;
+			snps,read-requests = <16>;
+			snps,burst-map = <0x7>;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			status = "disabled";
+		};
+
+		gpu: gpu@18000000 {
+			compatible = "img-gpu";
+			reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_GPU_CORE_CLK>, <&clkgen JH7110_GPU_SYS_CLK>;
+			clock-names = "gpu_core_clk","gpu_sys_clk";
+			interrupts = <82>;
+			current-clock = <8000000>;
+			status = "disabled";
+		};
+
+		ipmscan0: can@130d0000 {
+			compatible = "ipms,can";
+			reg = <0x0 0x130d0000 0x0 0x1000>,
+				<0x0 0x13030000 0x0 0x10000>;
+			reg-names = "reg_base","sys_syscon";
+			interrupts = <112>;
+			clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
+				<&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
+				<&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
+			clock-names = "apb_clk",
+					"core_clk",
+					"timer_clk";
+			resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
+				<&rstgen RSTN_U0_CAN_CTRL_CORE>,
+				<&rstgen RSTN_U0_CAN_CTRL_TIMER>;
+			reset-names = "rst_apb",
+					"rst_core",
+					"rst_timer";
+			status = "disabled";
+		};
+
+		ipmscan1: can@130c0000 {
+			compatible = "ipms,can";
+			reg = <0x0 0x130c0000 0x0 0x1000>,
+				<0x0 0x13030000 0x0 0x10000>;
+			reg-names = "reg_base","sys_syscon";
+			interrupts = <113>;
+			clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
+				<&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
+				<&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
+			clock-names = "apb_clk",
+					"core_clk",
+					"timer_clk";
+			resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
+				<&rstgen RSTN_U1_CAN_CTRL_CORE>,
+				<&rstgen RSTN_U1_CAN_CTRL_TIMER>;
+			reset-names = "rst_apb",
+					"rst_core",
+					"rst_timer";
+			status = "disabled";
+		};
+
+		tdm: tdm@10090000 {
+			compatible = "starfive,tdm";
+			reg = <0x0 0x10090000 0x0 0x1000>;
+			reg-names = "tdm";
+			clocks = <&clkgen JH7110_TDM_CLK_TDM>;
+			clock-names = "audioclk";
+			dmas = <&dma 20 1>, <&dma 21 1>;
+			dma-names = "rx","tx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		spdif0: spdif0@100a0000 {
+			compatible = "starfive,sf-spdif";
+			reg = <0x0 0x100a0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_SPDIF_CLK_CORE>;
+			clock-names = "audioclk";
+			interrupts = <84>;
+			interrupt-names = "tx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		pwmdac: pwmdac@100b0000 {
+			compatible = "sf,pwmdac";
+			reg = <0x0 0x100b0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_APB0>;
+			dmas = <&dma 22 1>;
+			dma-names = "tx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		i2stx: i2stx@100c0000 {
+			compatible = "snps,designware-i2stx";
+			reg = <0x0 0x100c0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_APB0>;
+			clock-names = "i2sclk";
+			interrupt-names = "tx";
+			#sound-dai-cells = <0>;
+			dmas = <&dma 28 1>;
+			dma-names = "rx";
+			status = "disabled";
+		};
+
+		pdm: pdm@100d0000 {
+			compatible = "starfive,sf-pdm";
+			reg = <0x0 0x100d0000 0x0 0x1000>;
+			reg-names = "pdm";
+			clocks = <&clkgen JH7110_PDM_CLK_DMIC>;
+			clock-names = "audioclk";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		i2srx_3ch: i2srx-3ch@100e0000 {
+			compatible = "snps,designware-i2srx";
+			reg = <0x0 0x100e0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_APB0>;
+			clock-names = "i2sclk";
+			interrupts = <42>;
+			interrupt-names = "rx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		i2stx_4ch0: i2stx-4ch0@120b0000 {
+			compatible = "snps,designware-i2stx-4ch0";
+			reg = <0x0 0x120b0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_APB0>;
+			clock-names = "i2sclk";
+			interrupts = <58>;
+			interrupt-names = "tx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		i2stx_4ch1: i2sdac1@120c0000 {
+			compatible = "snps,designware-i2stx-4ch1";
+			reg = <0x0 0x120c0000 0x0 0x1000>;
+			clocks = <&clkgen JH7110_APB0>;
+			clock-names = "i2sclk";
+			interrupts = <59>;
+			interrupt-names = "tx";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		ptc: pwm@120d0000 {
+			compatible = "starfive,pwm0";
+			reg = <0x0 0x120d0000 0x0 0x10000>;
+			reg-names = "control";
+			clocks = <&clkgen JH7110_PWM_CLK_APB>;
+			sifive,approx-period = <1000000>;
+			#pwm-cells=<3>;
+			sifive,npwm = <8>;
+			status = "disabled";
+		};
+
+		spdif_transmitter: spdif_transmitter {
+			compatible = "linux,spdif-dit";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		spdif_receiver: spdif_receiver {
+			compatible = "linux,spdif-dir";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		pwmdac_codec: pwmdac-transmitter {
+			compatible = "linux,pwmdac-dit";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		dmic_codec: dmic_codec {
+			compatible = "dmic-codec";
+			#sound-dai-cells = <0>;
+			status = "disabled";
+		};
+
+		spi0: spi0@10060000 {
+			compatible = "arm,pl022", "arm,primecell";
+			reg = <0x0 0x10060000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_AHB1>;
+			clock-names = "apb_pclk";
+			interrupts = <38>;
+			dmas = <&dma 14 1>, <&dma 15 1>;
+			dma-names = "rx","tx";
+			arm,primecell-periphid = <0x00041022>;
+			num-cs = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pcie0: pcie0@2B000000 {
+			compatible = "plda,pci-xpressrich3-axi";
+			reg = <0x0 0x2B000000 0x0 0x1000000
+					0x9 0x40000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			interrupts = <56>;
+			interrupt-controller;
+			interrupt-names = "msi";
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+							<0x0 0x0 0x0 0x2 &plic 0x2>,
+							<0x0 0x0 0x0 0x3 &plic 0x3>,
+							<0x0 0x0 0x0 0x4 &plic 0x4>;
+			#interrupt-cells = <1>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			msi-parent = <&plic>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			ranges = <0x82000000  0x0 0x30000000  0x0
+					0x30000000 0x0 0x06000000>;
+			status = "disabled";
+		};
+
+		mailbox_contrl0: mailbox@0 {
+			compatible = "starfive,mail_box";
+			reg = <0x0 0x13060000 0x0 0x0001000>;
+			interrupts = <26 27>;
+			#mbox-cells = <2>;
+			status = "disabled";
+		};
+
+		mailbox_client0: mailbox_client@0 {
+			compatible = "starfive,mailbox-test";
+			mbox-names = "rx", "tx";
+			mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
+			status = "disabled";
+		};
+
+		display: display-subsystem {
+			compatible = "verisilicon,display-subsystem";
+			ports = <&dc_out_dpi0>;
+			status = "disabled";
+		};
+
+		encoder: display-encoder {
+			compatible = "starfive,display-encoder";
+			status = "disabled";
+		};
+
+		dc8200@29400000 {
+			compatible = "verisilicon,dc8200";
+			reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
+			interrupts = <95>;
+
+			port {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				dc_out_dpi0: endpoint@0 {
+					/*reg = <0>;
+					remote-endpoint = <&hdmi_input>;*/
+				};
+				dc_out_dpi1: endpoint@1 {
+					/*reg = <1>;
+					remote-endpoint = <&vd_input>;*/
+				};
+			};
+		};
+
+		sound_pwmdac: snd-card_pwmdac {
+			compatible = "simple-audio-card";
+			simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
+			simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
+			simple-audio-card,frame-master = <&pwmdac_dailink_master>;
+			simple-audio-card,format = "left_j";
+			status = "disabled";
+
+			pwmdac_dailink_master: simple-audio-card,cpu {
+				sound-dai = <&clkgen JH7110_PWMDAC_CLK_CORE>;
+			};
+
+			simple-audio-card,codec {
+				sound-dai = <&pwmdac_codec>;
+			};
+		};
+	};
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi
new file mode 100644
index 0000000000..d67134fa8a
--- /dev/null
+++ b/arch/riscv/dts/jh7110_clk.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/ {
+	/* clock tree external clocks */
+	osc: osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+	};
+
+	gmac1_rmii_refin: gmac1_rmii_refin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	gmac1_rgmii_rxin: gmac1_rgmii_rxin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	i2stx_bclk_ext: i2stx_bclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	i2stx_lrck_ext: i2stx_lrck_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <192000>;
+	};
+
+	i2srx_bclk_ext: i2srx_bclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <12288000>;
+	};
+
+	i2srx_lrck_ext: i2srx_lrck_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <192000>;
+	};
+
+	tdm_ext: tdm_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <49152000>;
+	};
+
+	mclk_ext: mclk_ext {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <49152000>;
+	};
+
+	jtag_tck_inner: jtag_tck_inner {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	bist_apb: bist_apb {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	stg_apb: stg_apb {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <51200000>;
+	};
+
+	gmac0_rmii_refin: gmac0_rmii_refin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <50000000>;
+	};
+
+	gmac0_rgmii_rxin: gmac0_rgmii_rxin {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
+	clk_rtc: clk_rtc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
+	hdmitx0_pixelclk: hdmitx0_pixelclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <297000000>;
+	};
+
+	mipitx_dphy_rxesc: mipitx_dphy_rxesc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <10000000>;
+	};
+
+	mipitx_dphy_txbytehs: mipitx_dphy_txbytehs {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <297000000>;
+	};
+
+	/* external clocks end */
+};
diff --git a/arch/riscv/dts/starfive_visionfive-u-boot.dtsi b/arch/riscv/dts/starfive_visionfive-u-boot.dtsi
new file mode 100644
index 0000000000..a3efa43b5e
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive-u-boot.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "jh7110-u-boot.dtsi"
+/ {
+	chosen {
+			stdout-path = "/soc/serial@10000000:115200";
+			u-boot,dm-spl;
+	};
+
+	firmware {
+		spi0="/soc/qspi@11860000";
+		u-boot,dm-spl;
+	};
+
+	config {
+		u-boot,dm-spl;
+		u-boot,spl-payload-offset = <0x100000>; /* loader2 @1044KB */
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x1 0x0>;
+	};
+};
+
+&sdio0 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+};
+
+&sdio1 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+};
\ No newline at end of file
diff --git a/arch/riscv/dts/starfive_visionfive.dts b/arch/riscv/dts/starfive_visionfive.dts
new file mode 100644
index 0000000000..e5bb25042c
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "StarFive VisionFive V2";
+	compatible = "starfive,jh7110";
+
+	chosen {
+			stdout-path = "/soc/serial@10000000:115200";
+	};
+
+	aliases {
+		spi0="/soc/qspi@13010000";
+		gpio0="/soc/gpio@13040000";
+		ethernet0="/soc/gmac0@16030000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x1 0x0>;
+	};
+
+	soc {
+	};
+};
+
+&cpu0 {
+	status = "okay";
+};
+
+&clkgen {
+	clocks = <&osc>, <&gmac1_rmii_refin>,
+		<&stg_apb>, <&gmac0_rmii_refin>;
+	clock-names = "osc", "gmac1_rmii_refin",
+		"stg_apb", "gmac0_rmii_refin";
+};
+
+&sdio0 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdio1 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&gmac0 {
+	phy-reset-gpios = <&gpio 63 0>;
+	status = "okay";
+};
+
+&gpio {
+	compatible = "starfive,jh7110-gpio";
+	gpio-controller;
+};
+
+&uart0 {
+	reg-offset = <0>;
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&gpioa {
+	status = "disabled";
+};
+
+
+
+
+
+
+
+
+
+
+
+