diff options
| author | yanhong.wang <yanhong.wang@starfivetech.com> | 2022-05-15 09:58:51 +0300 |
|---|---|---|
| committer | Yanhong Wang <yanhong.wang@linux.starfivetech.com> | 2022-10-18 11:24:35 +0300 |
| commit | 6f0b30d82cebe9457d42f442846b716fcca65beb (patch) | |
| tree | 418160b2be3a5e447a435d503e6d861cc5d1b8d4 /arch/riscv | |
| parent | 0eddcac0de54ba6d7b73f4cef8fffc9ce86582e0 (diff) | |
| download | u-boot-6f0b30d82cebe9457d42f442846b716fcca65beb.tar.xz | |
riscv:dts:starfive-jh7110: add ddr device node
Add ddr device node for JH7110.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/dts/jh7110-u-boot.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi index e355f6a8af..bb24681cc2 100644 --- a/arch/riscv/dts/jh7110-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-u-boot.dtsi @@ -57,6 +57,13 @@ clint: clint@2000000 { u-boot,dm-spl; }; + + dmc: dmc@100b0000 { + compatible = "starfive,jh7110-ddr"; + reg = <0x0 0x15700000 0x0 0x10000 0x0 0x13000000 0x0 0x10000>; + clock-frequency = <2133>; + u-boot,dm-spl; + }; }; }; |