riscv:dts: update clk&reset properties

Synchronize the kernel dts file

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

2 files changed, 182 insertions, 53 deletions

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index f877cc627b..df51978360 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -175,6 +175,21 @@
 			cache-unified;
 		};
 
+		aon_syscon: aon_syscon@17010000 {
+			compatible = "syscon";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
+		stg_syscon: stg_syscon@10240000 {
+			compatible = "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
+		sys_syscon: sys_syscon@13030000 {
+			compatible = "syscon";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		clint: clint@2000000 {
 			compatible = "riscv,clint0";
 			reg = <0x0 0x2000000 0x0 0x10000>;
@@ -285,34 +300,54 @@
 			clock-names = "apb";
 		};
 
-		USB30: usb@10100000 {
-			compatible = "cdns,usb3";
-			reg = <0x0 0x10100000 0x0 0x10000>,
-				<0x0 0x10110000 0x0 0x10000>,
-				<0x0 0x10120000 0x0 0x10000>;
-			reg-names = "otg", "xhci", "dev";
-			phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+		usbdrd30: usbdrd{
+			compatible = "starfive,jh7110-cdns3";
+			#address-cells = <2>;
+			#size-cells = <2>;
 			clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
-				<&clkgen JH7110_USB0_CLK_LPM>,
-				<&clkgen JH7110_USB0_CLK_STB>,
-				<&clkgen JH7110_USB0_CLK_USB_APB>,
-				<&clkgen JH7110_USB0_CLK_AXI>,
-				<&clkgen JH7110_USB0_CLK_UTMI_APB>;
+					<&clkgen JH7110_USB0_CLK_LPM>,
+					<&clkgen JH7110_USB0_CLK_STB>,
+					<&clkgen JH7110_USB0_CLK_USB_APB>,
+					<&clkgen JH7110_USB0_CLK_AXI>,
+					<&clkgen JH7110_USB0_CLK_UTMI_APB>;
 			clock-names = "app","lpm","stb","apb","axi","utmi";
 			resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 					<&rstgen RSTN_U0_CDN_USB_APB>,
 					<&rstgen RSTN_U0_CDN_USB_AXI>,
 					<&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
-			reset-names = "rst_pweup","rst_apb","rst_axi","rst_utmi";
+			reset-names = "pwrup","apb","axi","utmi";
+			starfive,stg-syscon = <&stg_syscon 0x4>;
+			starfive,sys-syscon = <&sys_syscon 0x18>;
+			status = "disabled";
+
+			usbdrd_cdns3: usb@10100000 {
+				compatible = "cdns,usb3";
+				reg = <0x0 0x10100000 0x0 0x10000>,
+					<0x0 0x10110000 0x0 0x10000>,
+					<0x0 0x10120000 0x0 0x10000>;
+				reg-names = "otg", "xhci", "dev";
+				interrupts = <108>, <109>, <110>;
+				interrupt-names = "host", "peripheral", "otg";
+				phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+				maximum-speed = "super-speed";
+			};
 		};
 
 		timer: timer@13050000 {
 			compatible = "starfive,si5-timers";
 			reg = <0x0 0x13050000 0x0 0x10000>;
 			interrupts = <69>, <70>, <71> ,<72>;
-			interrupt-names = "timer0", "timer1", "timer2", "timer3";
+			interrupt-names = "timer0", "timer1",
+					  "timer2", "timer3";
+			clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
+				 <&clkgen JH7110_TIMER_CLK_TIMER1>,
+				 <&clkgen JH7110_TIMER_CLK_TIMER2>,
+				 <&clkgen JH7110_TIMER_CLK_TIMER3>,
+				 <&clkgen JH7110_TIMER_CLK_APB>;
+			clock-names = "timer0", "timer1",
+				      "timer2", "timer3", "apb_clk";
 			clock-frequency = <2000000>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		wdog: wdog@13070000 {
@@ -321,6 +356,12 @@
 			interrupts = <68>;
 			interrupt-names = "wdog";
 			clock-frequency = <2000000>;
+			clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
+				 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
+			clock-names = "core_clk", "apb_clk";
+			resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
+				 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
+			reset-names = "rst_apb", "rst_core";
 			timeout-sec = <15>;
 			status = "okay";
 		};
@@ -330,8 +371,13 @@
 			reg = <0x0 0x17040000 0x0 0x10000>;
 			interrupts = <10>, <11>, <12>;
 			interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
-			clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>, <&clkgen JH7110_RTC_HMS_CLK_CAL>;
+			clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
+				 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 			clock-names = "pclk", "cal_clk";
+			resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
+				 <&rstgen RSTN_U0_RTC_HMS_CAL>,
+				 <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
+			reset-names = "rst_apb", "rst_cal", "rst_osc";
 			rtc,cal-clock-freq = <1000000>;
 			status = "okay";
 		};
@@ -351,6 +397,7 @@
 			clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 					<&clkgen JH7110_UART0_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U0_DW_UART_APB>;
 			interrupts = <32>;
 			status = "disabled";
 		};
@@ -363,6 +410,7 @@
 			clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 					<&clkgen JH7110_UART1_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U1_DW_UART_APB>;
 			interrupts = <33>;
 			status = "disabled";
 		};
@@ -375,6 +423,7 @@
 			clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 					<&clkgen JH7110_UART2_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U2_DW_UART_APB>;
 			interrupts = <34>;
 			status = "disabled";
 		};
@@ -387,6 +436,7 @@
 			clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 					<&clkgen JH7110_UART3_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U3_DW_UART_APB>;
 			interrupts = <45>;
 			status = "disabled";
 		};
@@ -399,6 +449,7 @@
 			clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 					<&clkgen JH7110_UART4_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U4_DW_UART_APB>;
 			interrupts = <46>;
 			status = "disabled";
 		};
@@ -411,6 +462,7 @@
 			clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 					<&clkgen JH7110_UART5_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
+			resets = <&rstgen RSTN_U5_DW_UART_APB>;
 			interrupts = <47>;
 			status = "disabled";
 		};
@@ -418,8 +470,13 @@
 		dma: dma-controller@16050000 {
 			compatible = "starfive,axi-dma";
 			reg = <0x0 0x16050000 0x0 0x10000>;
-			clocks = <&clkgen JH7110_DMA1P_CLK_AHB>, <&clkgen JH7110_DMA1P_CLK_AXI>;
+			clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
+				<&clkgen JH7110_DMA1P_CLK_AHB>;
 			clock-names = "core-clk", "cfgr-clk";
+			resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
+				<&rstgen RSTN_U0_DW_DMA1P_AHB>;
+			reset-names = "rst_axi",
+				"rst_ahb";
 			interrupts = <73>;
 			#dma-cells = <2>;
 			dma-channels = <4>;
@@ -457,7 +514,10 @@
 		trng: trng@1600C000 {
 			compatible = "starfive,trng";
 			reg = <0x0 0x1600C000 0x0 0x4000>;
-			clocks = <&clkgen JH7110_APB12>;
+			clocks = <&clkgen JH7110_SEC_HCLK>,
+				<&clkgen JH7110_SEC_MISCAHB_CLK>;
+			clock-names = "hclk", "miscahb_clk";
+			resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 			interrupts = <30>;
 			status = "disabled";
 		};
@@ -465,6 +525,10 @@
 		i2c6: i2c@12060000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x12060000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
+				 <&clkgen JH7110_I2C6_CLK_APB>;
+			clock-names = "ref", "pclk";
+			resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 			interrupts = <51>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -474,6 +538,10 @@
 		i2c0: i2c@10030000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x10030000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
+				 <&clkgen JH7110_I2C0_CLK_APB>;
+			clock-names = "ref", "pclk";
+			resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 			interrupts = <35>;
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -483,18 +551,25 @@
 		i2c1: i2c@10040000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x10040000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
+				 <&clkgen JH7110_I2C1_CLK_APB>;
+			clock-names = "ref", "pclk";
+			resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 			interrupts = <36>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};
 
+		/* unremovable emmc as mmcblk0 */
 		sdio0: sdio0@16010000 {
 			compatible = "snps,dw-mshc";
 			reg = <0x0 0x16010000 0x0 0x10000>;
 			clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
-					<&clkgen JH7110_SDIO0_CLK_SDCARD>;
+				 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 			clock-names = "biu","ciu";
+			resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
+			reset-names = "reset";
 			interrupts = <74>;
 			fifo-depth = <32>;
 			fifo-watermark-aligned;
@@ -506,8 +581,10 @@
 			compatible = "snps,dw-mshc";
 			reg = <0x0 0x16020000 0x0 0x10000>;
 			clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
-					<&clkgen JH7110_SDIO1_CLK_SDCARD>;
+				 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 			clock-names = "biu","ciu";
+			resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
+			reset-names = "reset";
 			interrupts = <75>;
 			fifo-depth = <32>;
 			fifo-watermark-aligned;
@@ -539,17 +616,15 @@
 		jpu: jpu@11900000 {
 			compatible = "starfive,jpu";
 			reg = <0x0 0x13090000 0x0 0x300>;
+			interrupts = <14>;
 			clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
-					<&clkgen JH7110_CODAJ12_CLK_CORE>,
-					<&clkgen JH7110_CODAJ12_CLK_APB>;
+				<&clkgen JH7110_CODAJ12_CLK_CORE>,
+				<&clkgen JH7110_CODAJ12_CLK_APB>;
 			clock-names = "axi_clk", "core_clk", "apb_clk";
 			resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 				<&rstgen RSTN_U0_CODAJ12_CORE>,
 				<&rstgen RSTN_U0_CODAJ12_APB>;
-			reset-names = "rst_axi",
-				"rst_core",
-				"rst_apb";
-			interrupts = <14>;
+			reset-names = "rst_axi", "rst_core", "rst_apb";
 			status = "disabled";
 		};
 
@@ -627,7 +702,7 @@
 			snps,blen = <256 128 64 32 0 0 0>;
 		};
 
-		gmac0: gmac0@16030000 {
+		gmac0: ethernet@16030000 {
 			compatible = "starfive,jh7110-eqos-5.20";
 			reg = <0x0 0x16030000 0x0 0x10000>;
 			clock-names = "gtx",
@@ -666,7 +741,7 @@
 			status = "disabled";
 		};
 
-		gmac1: gmac01@16040000 {
+		gmac1: ethernet@16040000 {
 			compatible = "starfive,jh7110-eqos-5.20";
 			reg = <0x0 0x16040000 0x0 0x10000>;
 			clock-names = "gtx",
@@ -674,7 +749,7 @@
 				"ptp_ref",
 				"stmmaceth",
 				"pclk";
-			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
+			clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 				<&clkgen JH7110_GMAC5_CLK_TX>,
 				<&clkgen JH7110_GMAC5_CLK_PTP>,
 				<&clkgen JH7110_GMAC5_CLK_AHB>,
@@ -715,11 +790,9 @@
 			status = "disabled";
 		};
 
-		ipmscan0: can@130d0000 {
+		can0: can@130d0000 {
 			compatible = "ipms,can";
-			reg = <0x0 0x130d0000 0x0 0x1000>,
-				<0x0 0x13030000 0x0 0x10000>;
-			reg-names = "reg_base","sys_syscon";
+			reg = <0x0 0x130d0000 0x0 0x1000>;
 			interrupts = <112>;
 			clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
 				<&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
@@ -733,14 +806,14 @@
 			reset-names = "rst_apb",
 					"rst_core",
 					"rst_timer";
+			starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
+			syscon,can_or_canfd = <0>;
 			status = "disabled";
 		};
 
-		ipmscan1: can@130c0000 {
+		can1: can@130e0000 {
 			compatible = "ipms,can";
-			reg = <0x0 0x130c0000 0x0 0x1000>,
-				<0x0 0x13030000 0x0 0x10000>;
-			reg-names = "reg_base","sys_syscon";
+			reg = <0x0 0x130e0000 0x0 0x1000>;
 			interrupts = <113>;
 			clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
 				<&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
@@ -754,6 +827,8 @@
 			reset-names = "rst_apb",
 					"rst_core",
 					"rst_timer";
+			starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
+			syscon,can_or_canfd = <0>;
 			status = "disabled";
 		};
 
@@ -850,9 +925,10 @@
 			reg = <0x0 0x120d0000 0x0 0x10000>;
 			reg-names = "control";
 			clocks = <&clkgen JH7110_PWM_CLK_APB>;
-			sifive,approx-period = <1000000>;
+			resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
+			starfive,approx-period = <2000000>;
 			#pwm-cells=<3>;
-			sifive,npwm = <8>;
+			starfive,npwm = <8>;
 			status = "disabled";
 		};
 
@@ -898,24 +974,73 @@
 		pcie0: pcie0@2B000000 {
 			compatible = "plda,pci-xpressrich3-axi";
 			reg = <0x0 0x2B000000 0x0 0x1000000
-					0x9 0x40000000 0x0 0x10000000>;
+			       0x9 0x40000000 0x0 0x10000000>;
 			reg-names = "reg", "config";
 			interrupts = <56>;
 			interrupt-controller;
 			interrupt-names = "msi";
 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
-							<0x0 0x0 0x0 0x2 &plic 0x2>,
-							<0x0 0x0 0x0 0x3 &plic 0x3>,
-							<0x0 0x0 0x0 0x4 &plic 0x4>;
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
+				 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
+				 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
+				 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
+				 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
+				 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
+			reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+				      "rst_brg", "rst_core", "rst_apb";
+			clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
+				 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
+				 <&clkgen JH7110_PCIE0_CLK_APB>;
+			clock-names =  "tl", "axi_mst0", "apb";
 			#interrupt-cells = <1>;
 			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
 			bus-range = <0x0 0xff>;
 			msi-parent = <&plic>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			ranges = <0x82000000  0x0 0x30000000  0x0
-					0x30000000 0x0 0x06000000>;
+			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
+			status = "disabled";
+		};
+
+		pcie1:pcie1@2C000000 {
+			compatible = "plda,pci-xpressrich3-axi";
+			reg = <0x0 0x2C000000 0x0 0x1000000
+			       0x9 0xc0000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+			bus-range = <0x0 0xff>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
+			msi-parent = <&plic>;
+			interrupts = <57>;
+			interrupt-controller;
+			interrupt-names = "msi";
+			interrupt-parent = <&plic>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
+				 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
+				 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
+				 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
+				 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
+				 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
+			reset-names = "rst_mst0", "rst_slv0", "rst_slv",
+				      "rst_brg", "rst_core", "rst_apb";
+			clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
+				 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
+				 <&clkgen JH7110_PCIE1_CLK_APB>;
+			clock-names =  "tl", "axi_mst0", "apb";
 			status = "disabled";
 		};
 
diff --git a/arch/riscv/dts/starfive_visionfive.dts b/arch/riscv/dts/starfive_visionfive.dts
index e5bb25042c..234fcb7121 100644
--- a/arch/riscv/dts/starfive_visionfive.dts
+++ b/arch/riscv/dts/starfive_visionfive.dts
@@ -76,14 +76,18 @@
 	status = "disabled";
 };
 
+&usbdrd30 {
+	status = "okay";
+};
 
+&usbdrd_cdns3 {
+	dr_mode = "host";
+};
 
+&timer {
+	status = "disabled";
+};
 
-
-
-
-
-
-
-
-
+&wdog {
+	status = "disabled";
+};