riscv:dts: update clk&reset properties

Synchronize the kernel dts file

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>

2 files changed, 443 insertions, 157 deletions

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index df51978360..a7952031ce 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/reset/starfive-jh7110.h>
 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
 #include <dt-bindings/clock/starfive-jh7110-vout.h>
+#include <dt-bindings/clock/starfive-jh7110-isp.h>
 
 / {
 	compatible = "starfive,jh7110";
@@ -224,13 +225,13 @@
 				<0x0 0x17000000 0x0 0x10000>;
 			reg-names = "sys", "stg", "aon";
 			clocks = <&osc>, <&gmac1_rmii_refin>,
-				<&gmac1_rgmii_rxin>,
-				<&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
-				<&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				<&tdm_ext>, <&mclk_ext>,
-				<&jtag_tck_inner>, <&bist_apb>,
-				<&stg_apb>, <&clk_rtc>,
-				<&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+				 <&gmac1_rgmii_rxin>,
+				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&jtag_tck_inner>, <&bist_apb>,
+				 <&stg_apb>, <&clk_rtc>,
+				 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				"gmac1_rgmii_rxin",
 				"i2stx_bclk_ext", "i2stx_lrck_ext",
@@ -247,14 +248,14 @@
 			compatible = "starfive,jh7110-clk-vout";
 			reg = <0x0 0x295C0000 0x0 0x10000>;
 			reg-names = "vout";
-			clocks = <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
-				<&clkgen JH7110_VOUT_TOP_CLK_MIPIPHY_REF>,
-				<&clkgen JH7110_VOUT_TOP_CLK_MIPIPHY_REF>;
+			clocks = <&hdmitx0_pixelclk>,
+				 <&mipitx_dphy_rxesc>,
+				 <&mipitx_dphy_txbytehs>;
 			clock-names = "hdmitx0_pixelclk",
 				"mipitx_dphy_rxesc",
 				"mipitx_dphy_txbytehs";
 			#clock-cells = <1>;
-			status = "disabled";
+			status = "okay";
 		};
 
 		clkisp: clock-controller@19810000 {
@@ -262,11 +263,20 @@
 			reg = <0x0 0x19810000 0x0 0x10000>;
 			reg-names = "isp";
 			#clock-cells = <1>;
+			clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+				 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+				 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
+			clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+				      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+				      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
+			resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+				 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
+			reset-names = "rst_isp_top_n", "rst_isp_top_axi";
 			status = "disabled";
 		};
 
-		qspi: qspi@13010000 {
-			compatible = "cadence,qspi","cdns,qspi-nor";
+		qspi: spi@13010000 {
+			compatible = "cdns,qspi-nor";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0 0x13010000 0x0 0x10000
@@ -274,8 +284,8 @@
 			clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 			clock-names = "clk_ref";
 			resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
-					<&rstgen RSTN_U0_CDNS_QSPI_AHB>,
-					<&rstgen RSTN_U0_CDNS_QSPI_REF>;
+				 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
+				 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 			resets-names = "rst_apb", "rst_ahb", "rst_ref";
 			cdns,fifo-depth = <256>;
 			cdns,fifo-width = <4>;
@@ -305,16 +315,16 @@
 			#address-cells = <2>;
 			#size-cells = <2>;
 			clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
-					<&clkgen JH7110_USB0_CLK_LPM>,
-					<&clkgen JH7110_USB0_CLK_STB>,
-					<&clkgen JH7110_USB0_CLK_USB_APB>,
-					<&clkgen JH7110_USB0_CLK_AXI>,
-					<&clkgen JH7110_USB0_CLK_UTMI_APB>;
+				 <&clkgen JH7110_USB0_CLK_LPM>,
+				 <&clkgen JH7110_USB0_CLK_STB>,
+				 <&clkgen JH7110_USB0_CLK_USB_APB>,
+				 <&clkgen JH7110_USB0_CLK_AXI>,
+				 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 			clock-names = "app","lpm","stb","apb","axi","utmi";
 			resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
-					<&rstgen RSTN_U0_CDN_USB_APB>,
-					<&rstgen RSTN_U0_CDN_USB_AXI>,
-					<&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
+				 <&rstgen RSTN_U0_CDN_USB_APB>,
+				 <&rstgen RSTN_U0_CDN_USB_AXI>,
+				 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 			reset-names = "pwrup","apb","axi","utmi";
 			starfive,stg-syscon = <&stg_syscon 0x4>;
 			starfive,sys-syscon = <&sys_syscon 0x18>;
@@ -323,8 +333,8 @@
 			usbdrd_cdns3: usb@10100000 {
 				compatible = "cdns,usb3";
 				reg = <0x0 0x10100000 0x0 0x10000>,
-					<0x0 0x10110000 0x0 0x10000>,
-					<0x0 0x10120000 0x0 0x10000>;
+				      <0x0 0x10110000 0x0 0x10000>,
+				      <0x0 0x10120000 0x0 0x10000>;
 				reg-names = "otg", "xhci", "dev";
 				interrupts = <108>, <109>, <110>;
 				interrupt-names = "host", "peripheral", "otg";
@@ -395,7 +405,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART0_CLK_CORE>,
-					<&clkgen JH7110_UART0_CLK_APB>;
+				 <&clkgen JH7110_UART0_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U0_DW_UART_APB>;
 			interrupts = <32>;
@@ -408,7 +418,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART1_CLK_CORE>,
-					<&clkgen JH7110_UART1_CLK_APB>;
+				 <&clkgen JH7110_UART1_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U1_DW_UART_APB>;
 			interrupts = <33>;
@@ -421,7 +431,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART2_CLK_CORE>,
-					<&clkgen JH7110_UART2_CLK_APB>;
+				 <&clkgen JH7110_UART2_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U2_DW_UART_APB>;
 			interrupts = <34>;
@@ -434,7 +444,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART3_CLK_CORE>,
-					<&clkgen JH7110_UART3_CLK_APB>;
+				 <&clkgen JH7110_UART3_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U3_DW_UART_APB>;
 			interrupts = <45>;
@@ -447,7 +457,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART4_CLK_CORE>,
-					<&clkgen JH7110_UART4_CLK_APB>;
+				 <&clkgen JH7110_UART4_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U4_DW_UART_APB>;
 			interrupts = <46>;
@@ -460,7 +470,7 @@
 			reg-io-width = <4>;
 			reg-shift = <2>;
 			clocks = <&clkgen JH7110_UART5_CLK_CORE>,
-					<&clkgen JH7110_UART5_CLK_APB>;
+				 <&clkgen JH7110_UART5_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
 			resets = <&rstgen RSTN_U5_DW_UART_APB>;
 			interrupts = <47>;
@@ -471,12 +481,11 @@
 			compatible = "starfive,axi-dma";
 			reg = <0x0 0x16050000 0x0 0x10000>;
 			clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
-				<&clkgen JH7110_DMA1P_CLK_AHB>;
+				 <&clkgen JH7110_DMA1P_CLK_AHB>;
 			clock-names = "core-clk", "cfgr-clk";
 			resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
-				<&rstgen RSTN_U0_DW_DMA1P_AHB>;
-			reset-names = "rst_axi",
-				"rst_ahb";
+				 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
+			reset-names = "rst_axi", "rst_ahb";
 			interrupts = <73>;
 			#dma-cells = <2>;
 			dma-channels = <4>;
@@ -515,13 +524,51 @@
 			compatible = "starfive,trng";
 			reg = <0x0 0x1600C000 0x0 0x4000>;
 			clocks = <&clkgen JH7110_SEC_HCLK>,
-				<&clkgen JH7110_SEC_MISCAHB_CLK>;
+				 <&clkgen JH7110_SEC_MISCAHB_CLK>;
 			clock-names = "hclk", "miscahb_clk";
 			resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 			interrupts = <30>;
 			status = "disabled";
 		};
 
+		sec_dma: sec_dma@16008000 {
+			/*compatible = "arm,pl080", "arm,primecell";*/
+			compatible = "starfive,pl080";
+			reg = <0x0 0x16008000 0x0 0x4000>;
+			reg-names = "sec_dma";
+			interrupts = <29>;
+			clocks = <&clkgen JH7110_SEC_HCLK>,
+				 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+			clock-names = "sec_hclk","sec_ahb";
+			resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+			reset-names = "sec_hre";
+			lli-bus-interface-ahb1;
+			mem-bus-interface-ahb1;
+			memcpy-burst-size = <256>;
+			memcpy-bus-width = <32>;
+			#dma-cells = <2>;
+			status = "disabled";
+		};
+
+		crypto: crypto@16000000 {
+			compatible = "starfive,jh7110-sec";
+			reg = <0x0 0x16000000 0x0 0x4000>,
+			      <0x0 0x16008000 0x0 0x4000>;
+			reg-names = "secreg","secdma";
+			interrupts = <28>, <29>;
+			interrupt-names = "secirq", "dmairq";
+			clocks = <&clkgen JH7110_SEC_HCLK>,
+				 <&clkgen JH7110_SEC_MISCAHB_CLK>;
+			clock-names = "sec_hclk","sec_ahb";
+			resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
+			reset-names = "sec_hre";
+			enable-dma = "true";
+			dmas = <&sec_dma 1 2>,
+			       <&sec_dma 0 2>;
+			dma-names = "sec_m","sec_p";
+			status = "disabled";
+		};
+
 		i2c6: i2c@12060000 {
 			compatible = "snps,designware-i2c";
 			reg = <0x0 0x12060000 0x0 0x10000>;
@@ -601,14 +648,43 @@
 				<0x0 0x19840000 0x0 0x10000>,
 				<0x0 0x19870000 0x0 0x30000>,
 				<0x0 0x198a0000 0x0 0x30000>,
-				<0x0 0x11800000 0x0 0x10000>,
 				<0x0 0x11840000 0x0 0x10000>,
-				<0x0 0x11858000 0x0 0x10000>,
 				<0x0 0x17030000 0x0 0x10000>,
 				<0x0 0x13020000 0x0 0x10000>;
-			reg-names = "mipi0", "vclk", "vrst", "mipi1",
-				"sctrl", "isp0", "isp1", "tclk", "trst",
-				"iopad", "pmu", "syscrg";
+			reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
+				"isp0", "isp1", "trst", "pmu", "syscrg";
+			clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
+				 <&clkisp JH7110_U0_VIN_PCLK>,
+				 <&clkisp JH7110_U0_VIN_SYS_CLK>,
+				 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
+				 <&clkisp JH7110_DVP_INV>,
+				 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
+				 <&clkisp JH7110_MIPI_RX0_PXL>,
+				 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
+				 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
+				 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
+				 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
+			clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
+				"clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
+				"clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
+				"clk_pixel_clk_if1", "clk_pixel_clk_if2",
+				"clk_pixel_clk_if3";
+			resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
+				 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
+				 <&rstgen RSTN_U0_VIN_N_PCLK>,
+				 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
+				 <&rstgen RSTN_U0_VIN_P_AXIRD>,
+				 <&rstgen RSTN_U0_VIN_P_AXIWR>,
+				 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
+				 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
+				 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
+				 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
+				 <&rstgen RSTN_U0_M31DPHY_HW>,
+				 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>;
+			reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
+				"rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
+				"rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
+				"rst_m31dphy_hw", "rst_m31dphy_b09_always_on";
 			interrupts = <92 87 86>;
 			status = "disabled";
 		};
@@ -618,12 +694,12 @@
 			reg = <0x0 0x13090000 0x0 0x300>;
 			interrupts = <14>;
 			clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
-				<&clkgen JH7110_CODAJ12_CLK_CORE>,
-				<&clkgen JH7110_CODAJ12_CLK_APB>;
+				 <&clkgen JH7110_CODAJ12_CLK_CORE>,
+				 <&clkgen JH7110_CODAJ12_CLK_APB>;
 			clock-names = "axi_clk", "core_clk", "apb_clk";
 			resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
-				<&rstgen RSTN_U0_CODAJ12_CORE>,
-				<&rstgen RSTN_U0_CODAJ12_APB>;
+				 <&rstgen RSTN_U0_CODAJ12_CORE>,
+				 <&rstgen RSTN_U0_CODAJ12_APB>;
 			reset-names = "rst_axi", "rst_core", "rst_apb";
 			status = "disabled";
 		};
@@ -633,10 +709,10 @@
 			reg = <0x0 0x130A0000 0x0 0x10000>;
 			interrupts = <13>;
 			clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
-				<&clkgen JH7110_WAVE511_CLK_BPU>,
-				<&clkgen JH7110_WAVE511_CLK_VCE>,
-				<&clkgen JH7110_WAVE511_CLK_APB>,
-				<&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
+				 <&clkgen JH7110_WAVE511_CLK_BPU>,
+				 <&clkgen JH7110_WAVE511_CLK_VCE>,
+				 <&clkgen JH7110_WAVE511_CLK_APB>,
+				 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 			clock-names = "axi_clk",
 				"bpu_clk",
 				"vce_clk",
@@ -661,20 +737,20 @@
 			reg = <0x0 0x130B0000 0x0 0x10000>;
 			interrupts = <15>;
 			clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
-				<&clkgen JH7110_WAVE420L_CLK_BPU>,
-				<&clkgen JH7110_WAVE420L_CLK_VCE>,
-				<&clkgen JH7110_WAVE420L_CLK_APB>,
-				<&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
+				 <&clkgen JH7110_WAVE420L_CLK_BPU>,
+				 <&clkgen JH7110_WAVE420L_CLK_VCE>,
+				 <&clkgen JH7110_WAVE420L_CLK_APB>,
+				 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 			clock-names = "axi_clk",
 				"bpu_clk",
 				"vce_clk",
 				"apb_clk",
 				"noc_bus";
 			resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
-				<&rstgen RSTN_U0_WAVE420L_BPU>,
-				<&rstgen RSTN_U0_WAVE420L_VCE>,
-				<&rstgen RSTN_U0_WAVE420L_APB>,
-				<&rstgen RSTN_U1_AXIMEM_128B_AXI>;
+				 <&rstgen RSTN_U0_WAVE420L_BPU>,
+				 <&rstgen RSTN_U0_WAVE420L_VCE>,
+				 <&rstgen RSTN_U0_WAVE420L_APB>,
+				 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 			reset-names = "rst_axi",
 				"rst_bpu",
 				"rst_vce",
@@ -711,12 +787,12 @@
 				"stmmaceth",
 				"pclk";
 			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
-				<&clkgen JH7110_U0_GMAC5_CLK_TX>,
-				<&clkgen JH7110_GMAC0_PTP>,
-				<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
-				<&clkgen JH7110_U0_GMAC5_CLK_AXI>;
+				 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
+				 <&clkgen JH7110_GMAC0_PTP>,
+				 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
+				 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
 			resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
-					<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
+				 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 			reset-names = "ahb", "stmmaceth";
 			interrupts = <7>, <6>, <5> ;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -750,12 +826,12 @@
 				"stmmaceth",
 				"pclk";
 			clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
-				<&clkgen JH7110_GMAC5_CLK_TX>,
-				<&clkgen JH7110_GMAC5_CLK_PTP>,
-				<&clkgen JH7110_GMAC5_CLK_AHB>,
-				<&clkgen JH7110_GMAC5_CLK_AXI>;
+				 <&clkgen JH7110_GMAC5_CLK_TX>,
+				 <&clkgen JH7110_GMAC5_CLK_PTP>,
+				 <&clkgen JH7110_GMAC5_CLK_AHB>,
+				 <&clkgen JH7110_GMAC5_CLK_AXI>;
 			resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
-					<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
+				 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 			reset-names = "ahb", "stmmaceth";
 			interrupts = <78>, <77>, <76> ;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -782,9 +858,19 @@
 
 		gpu: gpu@18000000 {
 			compatible = "img-gpu";
-			reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
-			clocks = <&clkgen JH7110_GPU_CORE_CLK>, <&clkgen JH7110_GPU_SYS_CLK>;
-			clock-names = "gpu_core_clk","gpu_sys_clk";
+			reg = <0x0 0x18000000 0x0 0x100000>,
+				<0x0 0x130C000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_GPU_CLK_APB>,
+				<&clkgen JH7110_GPU_RTC_TOGGLE>,
+				<&clkgen JH7110_GPU_CORE_CLK>,
+				<&clkgen JH7110_GPU_SYS_CLK>,
+				<&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
+			clock-names = "clk_apb", "clk_rtc",
+				"clk_core", "clk_sys",
+				"clk_axi";
+			resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
+				 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
+			reset-names = "rst_apb", "rst_doma";
 			interrupts = <82>;
 			current-clock = <8000000>;
 			status = "disabled";
@@ -795,17 +881,13 @@
 			reg = <0x0 0x130d0000 0x0 0x1000>;
 			interrupts = <112>;
 			clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
-				<&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
-				<&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
-			clock-names = "apb_clk",
-					"core_clk",
-					"timer_clk";
+				 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
+				 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
+			clock-names = "apb_clk", "core_clk", "timer_clk";
 			resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
-				<&rstgen RSTN_U0_CAN_CTRL_CORE>,
-				<&rstgen RSTN_U0_CAN_CTRL_TIMER>;
-			reset-names = "rst_apb",
-					"rst_core",
-					"rst_timer";
+				 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
+				 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
+			reset-names = "rst_apb", "rst_core", "rst_timer";
 			starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
 			syscon,can_or_canfd = <0>;
 			status = "disabled";
@@ -816,28 +898,34 @@
 			reg = <0x0 0x130e0000 0x0 0x1000>;
 			interrupts = <113>;
 			clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
-				<&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
-				<&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
-			clock-names = "apb_clk",
-					"core_clk",
-					"timer_clk";
+				 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
+				 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
+			clock-names = "apb_clk", "core_clk", "timer_clk";
 			resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
-				<&rstgen RSTN_U1_CAN_CTRL_CORE>,
-				<&rstgen RSTN_U1_CAN_CTRL_TIMER>;
-			reset-names = "rst_apb",
-					"rst_core",
-					"rst_timer";
+				 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
+				 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
+			reset-names = "rst_apb", "rst_core", "rst_timer";
 			starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
 			syscon,can_or_canfd = <0>;
 			status = "disabled";
 		};
 
 		tdm: tdm@10090000 {
-			compatible = "starfive,tdm";
+			compatible = "starfive,sf-tdm";
 			reg = <0x0 0x10090000 0x0 0x1000>;
 			reg-names = "tdm";
-			clocks = <&clkgen JH7110_TDM_CLK_TDM>;
-			clock-names = "audioclk";
+			clocks = <&clkgen JH7110_AHB0>,
+				 <&clkgen JH7110_TDM_CLK_AHB>,
+				 <&clkgen JH7110_APB0>,
+				 <&clkgen JH7110_TDM_CLK_APB>,
+				 <&clkgen JH7110_TDM_INTERNAL>;
+			clock-names = "clk_ahb0", "clk_tdm_ahb",
+				      "clk_apb0", "clk_tdm_apb",
+				      "clk_tdm_intl";
+			resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
+				 <&rstgen RSTN_U0_TDM16SLOT_APB>,
+				 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
+			reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
 			dmas = <&dma 20 1>, <&dma 21 1>;
 			dma-names = "rx","tx";
 			#sound-dai-cells = <0>;
@@ -847,8 +935,12 @@
 		spdif0: spdif0@100a0000 {
 			compatible = "starfive,sf-spdif";
 			reg = <0x0 0x100a0000 0x0 0x1000>;
-			clocks = <&clkgen JH7110_SPDIF_CLK_CORE>;
-			clock-names = "audioclk";
+			clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
+				 <&clkgen JH7110_SPDIF_CLK_CORE>,
+				 <&clkgen JH7110_MCLK>;
+			clock-names = "spdif-apb", "spdif-core", "audioclk";
+			resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
+			reset-names = "rst_apb";
 			interrupts = <84>;
 			interrupt-names = "tx";
 			#sound-dai-cells = <0>;
@@ -856,9 +948,14 @@
 		};
 
 		pwmdac: pwmdac@100b0000 {
-			compatible = "sf,pwmdac";
+			compatible = "starfive,pwmdac";
 			reg = <0x0 0x100b0000 0x0 0x1000>;
-			clocks = <&clkgen JH7110_APB0>;
+			clocks = <&clkgen JH7110_APB0>,
+				 <&clkgen JH7110_PWMDAC_CLK_APB>,
+				 <&clkgen JH7110_PWMDAC_CLK_CORE>;
+			clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
+			resets = <&rstgen RSTN_U0_PWMDAC_APB>;
+			reset-names = "rst-apb";
 			dmas = <&dma 22 1>;
 			dma-names = "tx";
 			#sound-dai-cells = <0>;
@@ -881,41 +978,85 @@
 			compatible = "starfive,sf-pdm";
 			reg = <0x0 0x100d0000 0x0 0x1000>;
 			reg-names = "pdm";
-			clocks = <&clkgen JH7110_PDM_CLK_DMIC>;
-			clock-names = "audioclk";
+			clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
+				 <&clkgen JH7110_APB0>,
+				 <&clkgen JH7110_PDM_CLK_APB>,
+				 <&clkgen JH7110_PDM_CLK_DMIC0_BCLK_SLV>,
+				 <&clkgen JH7110_PDM_CLK_DMIC0_LRCK_SLV>,
+				 <&clkgen JH7110_PDM_CLK_DMIC1_BCLK_SLV>,
+				 <&clkgen JH7110_PDM_CLK_DMIC1_LRCK_SLV>,
+				 <&clkgen JH7110_I2SRX0_3CH_BCLK>;
+			clock-names = "pdm_dmic", "clk_apb0", "pdm_apb",
+					"pdm_dmic0_bclk", "pdm_dmic0_lrck",
+					"pdm_dmic1_bclk", "pdm_dmic1_lrck",
+					"u0_i2srx_3ch_bclk";
+			resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
+				 <&rstgen RSTN_U0_PDM_4MIC_APB>;
+			reset-names = "pdm_dmic", "pdm_apb";
 			#sound-dai-cells = <0>;
-			status = "disabled";
 		};
 
-		i2srx_3ch: i2srx-3ch@100e0000 {
+		i2srx_3ch: i2srx_3ch@100e0000 {
 			compatible = "snps,designware-i2srx";
 			reg = <0x0 0x100e0000 0x0 0x1000>;
-			clocks = <&clkgen JH7110_APB0>;
-			clock-names = "i2sclk";
+			clocks = <&clkgen JH7110_APB0>,
+				 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
+				 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>;
+			clock-names = "apb0", "3ch-apb",
+					"3ch-bclk";
+			resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
+				 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
+			reset-names = "rst_apb_rx", "rst_bclk_rx";
 			interrupts = <42>;
 			interrupt-names = "rx";
+			dmas = <&dma 24 1>;
+			dma-names = "rx";
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
 
-		i2stx_4ch0: i2stx-4ch0@120b0000 {
+		i2stx_4ch0: i2stx_4ch0@120b0000 {
 			compatible = "snps,designware-i2stx-4ch0";
 			reg = <0x0 0x120b0000 0x0 0x1000>;
-			clocks = <&clkgen JH7110_APB0>;
-			clock-names = "i2sclk";
+			clocks = <&clkgen JH7110_MCLK_INNER>,
+				 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
+				 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
+				 <&clkgen JH7110_MCLK>,
+				 <&clkgen JH7110_I2STX0_4CHBCLK>,
+				 <&clkgen JH7110_I2STX0_4CHLRCK>;
+			clock-names = "inner", "bclk-mst",
+					"lrck-mst", "mclk",
+					"bclk0", "lrck0";
+			resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
+				 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
+			reset-names = "rst_apb0", "rst_bclk0";
 			interrupts = <58>;
 			interrupt-names = "tx";
+			dmas = <&dma 47 1>;
+			dma-names = "tx";
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
 
-		i2stx_4ch1: i2sdac1@120c0000 {
+		i2stx_4ch1: i2stx_4ch1@120c0000 {
 			compatible = "snps,designware-i2stx-4ch1";
 			reg = <0x0 0x120c0000 0x0 0x1000>;
-			clocks = <&clkgen JH7110_APB0>;
-			clock-names = "i2sclk";
+			clocks = <&clkgen JH7110_MCLK_INNER>,
+				 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
+				 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
+				 <&clkgen JH7110_MCLK>,
+				 <&clkgen JH7110_I2STX1_4CHBCLK>,
+				 <&clkgen JH7110_I2STX1_4CHLRCK>;
+			clock-names = "inner", "bclk-mst1",
+					"lrck-mst1", "mclk",
+					"bclk1", "lrck1";
+			resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
+				 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
+			reset-names = "rst_apb1", "rst_bclk1";
 			interrupts = <59>;
 			interrupt-names = "tx";
+			dmas = <&dma 48 1>;
+			dma-names = "tx";
 			#sound-dai-cells = <0>;
 			status = "disabled";
 		};
@@ -956,11 +1097,13 @@
 			status = "disabled";
 		};
 
-		spi0: spi0@10060000 {
+		spi0: spi@10060000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x0 0x10060000 0x0 0x10000>;
-			clocks = <&clkgen JH7110_AHB1>;
+			clocks = <&clkgen JH7110_SPI0_CLK_APB>;
 			clock-names = "apb_pclk";
+			resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
+			reset-names = "rst_apb";
 			interrupts = <38>;
 			dmas = <&dma 14 1>, <&dma 15 1>;
 			dma-names = "rx","tx";
@@ -971,14 +1114,23 @@
 			status = "disabled";
 		};
 
-		pcie0: pcie0@2B000000 {
+		pcie0: pcie@2B000000 {
 			compatible = "plda,pci-xpressrich3-axi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
 			reg = <0x0 0x2B000000 0x0 0x1000000
 			       0x9 0x40000000 0x0 0x10000000>;
 			reg-names = "reg", "config";
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
+			msi-parent = <&plic>;
 			interrupts = <56>;
 			interrupt-controller;
 			interrupt-names = "msi";
+			interrupt-parent = <&plic>;
 			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 					<0x0 0x0 0x0 0x2 &plic 0x2>,
@@ -996,28 +1148,20 @@
 				 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
 				 <&clkgen JH7110_PCIE0_CLK_APB>;
 			clock-names =  "tl", "axi_mst0", "apb";
-			#interrupt-cells = <1>;
-			device_type = "pci";
-			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
-			bus-range = <0x0 0xff>;
-			msi-parent = <&plic>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
 			status = "disabled";
 		};
 
-		pcie1:pcie1@2C000000 {
+		pcie1: pcie@2C000000 {
 			compatible = "plda,pci-xpressrich3-axi";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
 			reg = <0x0 0x2C000000 0x0 0x1000000
 			       0x9 0xc0000000 0x0 0x10000000>;
 			reg-names = "reg", "config";
 			device_type = "pci";
 			starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
 			bus-range = <0x0 0xff>;
-			#address-cells = <3>;
-			#size-cells = <2>;
-			#interrupt-cells = <1>;
 			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
 			msi-parent = <&plic>;
 			interrupts = <57>;
@@ -1047,6 +1191,10 @@
 		mailbox_contrl0: mailbox@0 {
 			compatible = "starfive,mail_box";
 			reg = <0x0 0x13060000 0x0 0x0001000>;
+			clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
+			clock-names = "clk_apb";
+			resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
+			reset-names = "mbx_rre";
 			interrupts = <26 27>;
 			#mbox-cells = <2>;
 			status = "disabled";
@@ -1059,51 +1207,178 @@
 			status = "disabled";
 		};
 
-		display: display-subsystem {
-			compatible = "verisilicon,display-subsystem";
-			ports = <&dc_out_dpi0>;
-			status = "disabled";
+		dssctrl: dssctrl@295B0000 {
+			compatible = "verisilicon,dss-ctrl", "syscon";
+			reg = <0 0x295B0000 0 0x90>;
 		};
 
-		encoder: display-encoder {
-			compatible = "starfive,display-encoder";
+		hdmi_output: hdmi-output {
+			compatible = "verisilicon,hdmi-encoder";
+			verisilicon,dss-syscon = <&dssctrl>;
+			verisilicon,mux-mask = <0x70 0x380>;
+			verisilicon,mux-val = <0x40 0x280>;
 			status = "disabled";
 		};
 
-		dc8200@29400000 {
+		dc8200: dc8200@29400000 {
 			compatible = "verisilicon,dc8200";
-			reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
+			reg = <0x0 0x29400000 0x0 0x100>,
+			      <0x0 0x29400800 0x0 0x2000>,
+			      <0x0 0x17030000 0x0 0x1000>;
 			interrupts = <95>;
+			status = "disabled";
+			clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
+				 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
+				 <&clkgen JH7110_VOUT_SRC>,
+				 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
+				 <&clkgen JH7110_AHB1>,
+				 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
+				 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
+				 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
+				 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
+				 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
+				 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
+				 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
+				 <&clkvout JH7110_U0_DC8200_CLK_AHB>;
+			clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
+					"noc_disp","noc_isp","noc_stg","vout_src",
+					"top_vout_axi","ahb1","top_vout_ahb",
+					"top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
+					"axi_clk","core_clk","vout_ahb";
+
+			resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
+				 <&rstgen RSTN_U0_DC8200_AXI>,
+				 <&rstgen RSTN_U0_DC8200_AHB>,
+				 <&rstgen RSTN_U0_DC8200_CORE>,
+				 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
+				 <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
+				 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
+				 <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
+			reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
+					"rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
+					"rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
+					"rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
+		};
+
+		mipi_dphy: mipi-dphy@295e0000{
+			compatible = "starfive,jh7100-mipi-dphy-tx";
+			reg = <0x0 0x295e0000 0x0 0x10000>;
+			clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
+			clock-names = "dphy_txesc";
+			resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
+				 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
+			reset-names = "dphy_sys", "dphy_txbytehs";
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		 mipi_dsi: mipi@295d0000 {
+			compatible = "cdns,dsi";
+			reg = <0x0 0x295d0000 0x0 0x10000>;
+			reg-names = "dsi";
+			clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
+				 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
+				 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
+				 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
+			clock-names = "sys", "apb", "txesc", "dpi";
+			resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
+				 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
+				 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
+				 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
+				 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
+				 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
+			reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
+					"dsi_sys", "dsi_txbytehs", "dsi_txesc";
+			phys = <&mipi_dphy>;
+			phy-names = "dphy";
+			status = "disabled";
 
 			port {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				dc_out_dpi0: endpoint@0 {
-					/*reg = <0>;
-					remote-endpoint = <&hdmi_input>;*/
-				};
-				dc_out_dpi1: endpoint@1 {
-					/*reg = <1>;
-					remote-endpoint = <&vd_input>;*/
+				dsi_out_port: endpoint {
+					/*remote-endpoint = <&panel_dsi_port>;*/
 				};
 			};
+
+			mipi_panel: panel@0 {
+				/*compatible = "";*/
+				status = "disabled";
+			};
 		};
 
-		sound_pwmdac: snd-card_pwmdac {
-			compatible = "simple-audio-card";
-			simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
-			simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
-			simple-audio-card,frame-master = <&pwmdac_dailink_master>;
-			simple-audio-card,format = "left_j";
+		hdmi: hdmi@29590000 {
+			compatible = "rockchip,rk3036-inno-hdmi";
+			reg = <0x0 0x29590000 0x0 0x4000>;
+			/*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
+			/*clocks = <&cru  PCLK_HDMI>;*/
+			/*clock-names = "pclk";*/
+			/*pinctrl-names = "default";*/
+			/*pinctrl-0 = <&hdmi_ctl>;*/
 			status = "disabled";
+			clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
+				 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
+				 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
+			clock-names = "sysclk", "mclk", "bclk";
+			resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
+			reset-names = "hdmi_tx";
+		};
 
-			pwmdac_dailink_master: simple-audio-card,cpu {
-				sound-dai = <&clkgen JH7110_PWMDAC_CLK_CORE>;
-			};
+		sound: snd-card {
+			compatible = "simple-audio-card";
+			simple-audio-card,name = "Starfive-Multi-Sound-Card";
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-			simple-audio-card,codec {
-				sound-dai = <&pwmdac_codec>;
+			simple-audio-card,dai-link@0 {
+				reg = <0>;
+				format = "left_j";
+				bitclock-master = <&sndcpu0>;
+				frame-master = <&sndcpu0>;
+				status = "okay";
+
+				sndcpu0: cpu {
+					sound-dai = <&pwmdac>;
+				};
+
+				codec {
+					sound-dai = <&pwmdac_codec>;
+				};
 			};
 		};
+
+		co_process: e24@0 {
+			compatible = "starfive,e24";
+			reg = <0x0 0xc0110000 0x0 0x00001000>,
+				<0x0 0xc0111000 0x0 0x0001f000>;
+			reg-names = "ecmd", "espace";
+			clocks = <&clkgen JH7110_E2_RTC_CLK>,
+				 <&clkgen JH7110_E2_CLK_CORE>,
+				 <&clkgen JH7110_E2_CLK_DBG>;
+			clock-names = "clk_rtc", "clk_core", "clk_dbg";
+			resets = <&rstgen RSTN_U0_E24_CORE>;
+			reset-names = "e24_core";
+			starfive,stg-syscon = <&stg_syscon>;
+			interrupt-parent = <&plic>;
+			firmware-name = "e24_elf";
+			irq-mode = <1>;
+			mbox-names = "tx", "rx";
+			mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
+			status = "disabled";
+			dsp@0 {};
+		};
 	};
 };
\ No newline at end of file
diff --git a/arch/riscv/dts/starfive_visionfive.dts b/arch/riscv/dts/starfive_visionfive.dts
index 234fcb7121..70eb2567b8 100644
--- a/arch/riscv/dts/starfive_visionfive.dts
+++ b/arch/riscv/dts/starfive_visionfive.dts
@@ -12,15 +12,18 @@
 	model = "StarFive VisionFive V2";
 	compatible = "starfive,jh7110";
 
+	aliases {
+		spi0="/soc/spi@13010000";
+		gpio0="/soc/gpio@13040000";
+		ethernet0="/soc/ethernet@16030000";
+		mmc0="/soc/sdio0@16010000";
+		mmc1="/soc/sdio1@16020000";
+	};
+
 	chosen {
 			stdout-path = "/soc/serial@10000000:115200";
 	};
 
-	aliases {
-		spi0="/soc/qspi@13010000";
-		gpio0="/soc/gpio@13040000";
-		ethernet0="/soc/gmac0@16030000";
-	};
 
 	memory@80000000 {
 		device_type = "memory";
@@ -91,3 +94,11 @@
 &wdog {
 	status = "disabled";
 };
+
+&clkvout {
+	status = "disabled";
+};
+
+&pdm {
+	status = "disabled";
+};